coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
romstage.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <string.h>
4 #include <soc/romstage.h>
5 #include <fsp/api.h>
6 #include <FspmUpd.h>
7 
8 static const uint8_t Ch0_Bit_swizzling[] = {
9  0x09, 0x0e, 0x0c, 0x0d, 0x0a, 0x0b, 0x08, 0x0f,
10  0x05, 0x06, 0x01, 0x00, 0x02, 0x07, 0x04, 0x03,
11  0x1a, 0x1f, 0x1c, 0x1b, 0x1d, 0x19, 0x18, 0x1e,
12  0x14, 0x16, 0x17, 0x11, 0x12, 0x13, 0x10, 0x15
13 };
14 static const uint8_t Ch1_Bit_swizzling[] = {
15  0x06, 0x07, 0x05, 0x04, 0x03, 0x01, 0x00, 0x02,
16  0x0c, 0x0a, 0x0b, 0x0d, 0x0e, 0x08, 0x09, 0x0f,
17  0x14, 0x10, 0x16, 0x15, 0x12, 0x11, 0x13, 0x17,
18  0x1e, 0x1c, 0x1d, 0x19, 0x18, 0x1a, 0x1b, 0x1f
19 };
20 static const uint8_t Ch2_Bit_swizzling[] = {
21  0x0f, 0x09, 0x08, 0x0b, 0x0c, 0x0d, 0x0e, 0x0a,
22  0x05, 0x02, 0x00, 0x03, 0x06, 0x07, 0x01, 0x04,
23  0x19, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, 0x18, 0x1d,
24  0x14, 0x17, 0x16, 0x15, 0x12, 0x13, 0x10, 0x11
25 };
26 static const uint8_t Ch3_Bit_swizzling[] = {
27  0x03, 0x04, 0x06, 0x05, 0x00, 0x01, 0x02, 0x07,
28  0x0b, 0x0a, 0x08, 0x09, 0x0e, 0x0c, 0x0f, 0x0d,
29  0x11, 0x17, 0x13, 0x10, 0x15, 0x16, 0x14, 0x12,
30  0x1c, 0x1d, 0x1a, 0x19, 0x1e, 0x1b, 0x18, 0x1f
31 };
32 
33 void mainboard_memory_init_params(FSPM_UPD *memupd)
34 {
35  /* DRAM Config settings */
36  memupd->FspmConfig.Package = 0x1;
37  memupd->FspmConfig.Profile = 0xB;
38  memupd->FspmConfig.MemoryDown = 0x1;
39  memupd->FspmConfig.DDR3LPageSize = 0x0;
40  memupd->FspmConfig.DDR3LASR = 0x0;
41  memupd->FspmConfig.ScramblerSupport = 0x1;
42  memupd->FspmConfig.ChannelHashMask = 0x36;
43  memupd->FspmConfig.SliceHashMask = 0x9;
44  memupd->FspmConfig.InterleavedMode = 0x2;
45  memupd->FspmConfig.ChannelsSlicesEnable = 0x0;
46  memupd->FspmConfig.MinRefRate2xEnable = 0x0;
47  memupd->FspmConfig.DualRankSupportEnable = 0x0;
48  memupd->FspmConfig.RmtMode = 0x0;
49  memupd->FspmConfig.MemorySizeLimit = 0x1800;
50  memupd->FspmConfig.LowMemoryMaxValue = 0x0;
51  memupd->FspmConfig.DisableFastBoot = 0x0;
52  memupd->FspmConfig.HighMemoryMaxValue = 0x0;
53  memupd->FspmConfig.DIMM0SPDAddress = 0x0;
54  memupd->FspmConfig.DIMM1SPDAddress = 0x0;
55  memupd->FspmConfig.Ch0_RankEnable = 0x1;
56  memupd->FspmConfig.Ch0_DeviceWidth = 0x1;
57  memupd->FspmConfig.Ch0_DramDensity = 0x2;
58  memupd->FspmConfig.Ch0_Option = 0x3;
59  memupd->FspmConfig.Ch0_OdtConfig = 0x0;
60  memupd->FspmConfig.Ch0_TristateClk1 = 0x0;
61  memupd->FspmConfig.Ch0_Mode2N = 0x0;
62  memupd->FspmConfig.Ch0_OdtLevels = 0x0;
63  memupd->FspmConfig.Ch1_RankEnable = 0x1;
64  memupd->FspmConfig.Ch1_DeviceWidth = 0x1;
65  memupd->FspmConfig.Ch1_DramDensity = 0x2;
66  memupd->FspmConfig.Ch1_Option = 0x3;
67  memupd->FspmConfig.Ch1_OdtConfig = 0x0;
68  memupd->FspmConfig.Ch1_TristateClk1 = 0x0;
69  memupd->FspmConfig.Ch1_Mode2N = 0x0;
70  memupd->FspmConfig.Ch1_OdtLevels = 0x0;
71  memupd->FspmConfig.Ch2_RankEnable = 0x1;
72  memupd->FspmConfig.Ch2_DeviceWidth = 0x1;
73  memupd->FspmConfig.Ch2_DramDensity = 0x2;
74  memupd->FspmConfig.Ch2_Option = 0x3;
75  memupd->FspmConfig.Ch2_OdtConfig = 0x0;
76  memupd->FspmConfig.Ch2_TristateClk1 = 0x0;
77  memupd->FspmConfig.Ch2_Mode2N = 0x0;
78  memupd->FspmConfig.Ch2_OdtLevels = 0x0;
79  memupd->FspmConfig.Ch3_RankEnable = 0x1;
80  memupd->FspmConfig.Ch3_DeviceWidth = 0x1;
81  memupd->FspmConfig.Ch3_DramDensity = 0x2;
82  memupd->FspmConfig.Ch3_Option = 0x3;
83  memupd->FspmConfig.Ch3_OdtConfig = 0x0;
84  memupd->FspmConfig.Ch3_TristateClk1 = 0x0;
85  memupd->FspmConfig.Ch3_Mode2N = 0x0;
86  memupd->FspmConfig.Ch3_OdtLevels = 0x0;
87  memupd->FspmConfig.RmtCheckRun = 0x0;
88  memupd->FspmConfig.MrcDataSaving = 0x0;
89  memupd->FspmConfig.MrcFastBoot = 0x0;
90 
91  memcpy(memupd->FspmConfig.Ch0_Bit_swizzling, &Ch0_Bit_swizzling,
92  sizeof(Ch0_Bit_swizzling));
93  memcpy(memupd->FspmConfig.Ch1_Bit_swizzling, &Ch1_Bit_swizzling,
94  sizeof(Ch1_Bit_swizzling));
95  memcpy(memupd->FspmConfig.Ch2_Bit_swizzling, &Ch2_Bit_swizzling,
96  sizeof(Ch2_Bit_swizzling));
97  memcpy(memupd->FspmConfig.Ch3_Bit_swizzling, &Ch3_Bit_swizzling,
98  sizeof(Ch3_Bit_swizzling));
99 
100  memupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0x0;
101  memupd->FspmConfig.MsgLevelMask = 0x0;
102 }
void * memcpy(void *dest, const void *src, size_t n)
Definition: memcpy.c:7
void mainboard_memory_init_params(FSPM_UPD *mupd)
Definition: romstage.c:22
static const uint8_t Ch3_Bit_swizzling[]
Definition: romstage.c:26
static const uint8_t Ch0_Bit_swizzling[]
Definition: romstage.c:8
static const uint8_t Ch2_Bit_swizzling[]
Definition: romstage.c:20
static const uint8_t Ch1_Bit_swizzling[]
Definition: romstage.c:14
unsigned char uint8_t
Definition: stdint.h:8