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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include "chip.h"
#include <console/console.h>
#include <device/mmio.h>
#include <device/device.h>
#include <device/pci.h>
#include <intelblocks/pmc.h>
#include <intelblocks/pmclib.h>
#include <soc/iomap.h>
#include <soc/pm.h>
#include <timer.h>
Go to the source code of this file.
Functions | |
int | pmc_soc_get_resources (struct pmc_resource_config *cfg) |
static int | choose_slp_s3_assertion_width (int width_usecs) |
static void | set_slp_s3_assertion_width (int width_usecs) |
void | pmc_soc_init (struct device *dev) |
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Definition at line 27 of file pmc.c.
References ARRAY_SIZE, BIOS_DEBUG, printk, SLP_S3_ASSERT_1_MSEC, SLP_S3_ASSERT_2_SEC, SLP_S3_ASSERT_50_MSEC, SLP_S3_ASSERT_60_USEC, USECS_PER_MSEC, USECS_PER_SEC, and value.
Referenced by set_slp_s3_assertion_width().
int pmc_soc_get_resources | ( | struct pmc_resource_config * | cfg | ) |
Definition at line 15 of file pmc.c.
References pmc_resource_config::abase_addr, pmc_resource_config::abase_offset, pmc_resource_config::abase_size, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, PCH_PWRM_BASE_ADDRESS, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_4, PMC_BAR0_SIZE, pmc_resource_config::pwrmbase_addr, pmc_resource_config::pwrmbase_offset, and pmc_resource_config::pwrmbase_size.
Referenced by pch_pmc_read_resources().
Definition at line 80 of file pmc.c.
References config_of(), NULL, pch_log_state(), pmc_clear_prsts(), pmc_gpe_init(), pmc_set_acpi_mode(), pmc_set_power_failure_state(), set_slp_s3_assertion_width(), and soc_intel_apollolake_config::slp_s3_assertion_width_usecs.
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Definition at line 68 of file pmc.c.
References choose_slp_s3_assertion_width(), GEN_PMCON3, read32p(), SLP_S3_ASSERT_MASK, SLP_S3_ASSERT_WIDTH_SHIFT, soc_read_pmc_base(), and write32p().
Referenced by pmc_soc_init().