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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <baseboard/variants.h>
#include <bootmode.h>
#include <chip.h>
#include <console/console.h>
#include <delay.h>
#include <device/device.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <ec/google/chromeec/ec.h>
#include <gpio.h>
#include <intelblocks/power_limit.h>
#include <soc/pci_devs.h>
#include <timer.h>
Go to the source code of this file.
Macros | |
#define | GPIO_HDMI_HPD GPP_E13 |
#define | GPIO_DP_HPD GPP_E14 |
#define | SET_PSYSPL2(w) (97 * (w) / 100) |
#define | PUFF_U22_PL2 (35) |
#define | PUFF_U62_U42_PL2 (51) |
#define | PUFF_CELERON_PENTIUM_PSYSPL2 (65) |
#define | PUFF_CORE_CPU_PSYSPL2 (90) |
#define | PUFF_MAX_TIME_WINDOW 6 |
#define | PUFF_MIN_DUTYCYCLE 4 |
#define | PSYS_IMAX 9600 |
#define | BJ_VOLTS_MV 19000 |
Functions | |
static void | wait_for_hpd (gpio_t gpio, long timeout) |
static void | mainboard_set_power_limits (struct soc_power_limits_config *conf) |
void | variant_ramstage_init (void) |
#define BJ_VOLTS_MV 19000 |
Definition at line 89 of file mainboard.c.
#define GPIO_DP_HPD GPP_E14 |
Definition at line 18 of file mainboard.c.
#define GPIO_HDMI_HPD GPP_E13 |
Definition at line 17 of file mainboard.c.
#define PSYS_IMAX 9600 |
Definition at line 88 of file mainboard.c.
#define PUFF_CELERON_PENTIUM_PSYSPL2 (65) |
Definition at line 46 of file mainboard.c.
#define PUFF_CORE_CPU_PSYSPL2 (90) |
Definition at line 47 of file mainboard.c.
#define PUFF_MAX_TIME_WINDOW 6 |
Definition at line 48 of file mainboard.c.
#define PUFF_MIN_DUTYCYCLE 4 |
Definition at line 49 of file mainboard.c.
#define PUFF_U22_PL2 (35) |
Definition at line 44 of file mainboard.c.
#define PUFF_U62_U42_PL2 (51) |
Definition at line 45 of file mainboard.c.
#define SET_PSYSPL2 | ( | w | ) | (97 * (w) / 100) |
Definition at line 43 of file mainboard.c.
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static |
Definition at line 91 of file mainboard.c.
References BJ_VOLTS_MV, google_chromeec_get_usb_pd_power_info(), PCI_DEVICE_ID, PCI_DID_INTEL_CML_GT1_ULT_1, PCI_DID_INTEL_CML_GT2_ULT_5, PCI_DID_INTEL_CML_ULT, PCI_DID_INTEL_CML_ULT_6_2, pci_read_config16(), pcidev_path_on_root(), PSYS_IMAX, soc_power_limits_config::psys_pmax, PUFF_CELERON_PENTIUM_PSYSPL2, PUFF_CORE_CPU_PSYSPL2, PUFF_MAX_TIME_WINDOW, PUFF_MIN_DUTYCYCLE, PUFF_U22_PL2, PUFF_U62_U42_PL2, SA_DEVFN_IGD, SA_DEVFN_ROOT, SET_PSYSPL2, soc_power_limits_config::tdp_pl2_override, soc_power_limits_config::tdp_pl4, soc_power_limits_config::tdp_psyspl2, soc_power_limits_config::tdp_psyspl3, soc_power_limits_config::tdp_psyspl3_dutycycle, soc_power_limits_config::tdp_psyspl3_time, type, and USB_CHG_TYPE_PD.
Referenced by variant_ramstage_init().
Definition at line 152 of file mainboard.c.
References config_of_soc, display_init_required(), google_chromeec_wait_for_displayport(), GPIO_DP_HPD, gpio_get(), GPIO_HDMI_HPD, gpio_input(), mainboard_set_power_limits(), and wait_for_hpd().
Referenced by mainboard_enable().
Definition at line 21 of file mainboard.c.
References BIOS_INFO, BIOS_WARNING, gpio_get(), mdelay(), printk, stopwatch_duration_msecs(), stopwatch_expired(), and stopwatch_init_msecs_expire().
Referenced by variant_ramstage_init().