coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
irq_tables.c
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #include <arch/pirq_routing.h>
4 
5 static const struct irq_routing_table intel_irq_routing_table = {
8  32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
9  0x00, /* Interrupt router bus */
10  (0x04 << 3) | 0x0, /* Interrupt router device */
11  0, /* IRQs devoted exclusively to PCI usage */
12  0x8086, /* Vendor */
13  0x122e, /* Device */
14  0, /* Miniport data */
15  { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
16  0x54, /* Checksum */
17  /* clang-format off */
18  {
19  /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
20  {0x00,(0x0c << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x1, 0x0},
21  {0x00,(0x0b << 3)|0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x01eb8}}, 0x2, 0x0},
22  {0x00,(0x0a << 3)|0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x01eb8}}, 0x3, 0x0},
23  {0x00,(0x09 << 3)|0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x01eb8}}, 0x4, 0x0},
24  {0x00,(0x04 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
25  {0x00,(0x01 << 3)|0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x01eb8}}, 0x0, 0x0},
26  }
27  /* clang-format on */
28 };
29 
30 unsigned long write_pirq_routing_table(unsigned long addr)
31 {
33 }
unsigned long write_pirq_routing_table(unsigned long addr)
Definition: irq_tables.c:28
const struct irq_routing_table intel_irq_routing_table
Definition: irq_tables.c:5
static u32 addr
Definition: cirrus.c:14
#define PIRQ_SIGNATURE
Definition: pirq_routing.h:17
unsigned long copy_pirq_routing_table(unsigned long addr, const struct irq_routing_table *routing_table)
Definition: pirq_routing.c:172
#define PIRQ_VERSION
Definition: pirq_routing.h:18