coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
cirrus.c File Reference
#include <stdint.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <pc80/vga.h>
#include <pc80/vga_io.h>
#include <framebuffer_info.h>
Include dependency graph for cirrus.c:

Go to the source code of this file.

Macros

#define VGA_IO_MISC_COLOR   0x01
 
#define VGA_CR_WIDTH_DIVISOR   8
 
#define VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END1_SHIFT   7
 
#define VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END1_MASK   0x02
 
#define VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END2_SHIFT   3
 
#define VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END2_MASK   0x40
 
#define VGA_CR_OVERFLOW_VERT_TOTAL1_SHIFT   8
 
#define VGA_CR_OVERFLOW_VERT_TOTAL1_MASK   0x01
 
#define VGA_CR_OVERFLOW_VERT_TOTAL2_SHIFT   4
 
#define VGA_CR_OVERFLOW_VERT_TOTAL2_MASK   0x20
 
#define VGA_CR_OVERFLOW_VSYNC_START1_SHIFT   6
 
#define VGA_CR_OVERFLOW_VSYNC_START1_MASK   0x04
 
#define VGA_CR_OVERFLOW_VSYNC_START2_SHIFT   2
 
#define VGA_CR_OVERFLOW_VSYNC_START2_MASK   0x80
 
#define VGA_CR_OVERFLOW_HEIGHT1_SHIFT   7
 
#define VGA_CR_OVERFLOW_HEIGHT1_MASK   0x02
 
#define VGA_CR_OVERFLOW_HEIGHT2_SHIFT   3
 
#define VGA_CR_OVERFLOW_HEIGHT2_MASK   0xc0
 
#define VGA_CR_OVERFLOW_LINE_COMPARE_SHIFT   4
 
#define VGA_CR_OVERFLOW_LINE_COMPARE_MASK   0x10
 
#define VGA_CR_CELL_HEIGHT_LINE_COMPARE_MASK   0x40
 
#define VGA_CR_CELL_HEIGHT_LINE_COMPARE_SHIFT   3
 
#define VGA_CR_CELL_HEIGHT_VERTICAL_BLANK_MASK   0x20
 
#define VGA_CR_CELL_HEIGHT_VERTICAL_BLANK_SHIFT   4
 
#define VGA_CR_CELL_HEIGHT_DOUBLE_SCAN   0x80
 
#define VGA_CR_PITCH_DIVISOR   8
 
#define CIRRUS_CR_EXTENDED_DISPLAY   0x1b
 
#define CIRRUS_CR_EXTENDED_OVERLAY   0x1d
 
#define CIRRUS_CR_EXTENDED_DISPLAY_PITCH_MASK   0x10
 
#define CIRRUS_CR_EXTENDED_DISPLAY_PITCH_SHIFT   4
 
#define CIRRUS_CR_EXTENDED_DISPLAY_START_MASK1   0x1
 
#define CIRRUS_CR_EXTENDED_DISPLAY_START_SHIFT1   16
 
#define CIRRUS_CR_EXTENDED_DISPLAY_START_MASK2   0xc
 
#define CIRRUS_CR_EXTENDED_DISPLAY_START_SHIFT2   15
 
#define CIRRUS_CR_EXTENDED_OVERLAY_DISPLAY_START_MASK   0x80
 
#define CIRRUS_CR_EXTENDED_OVERLAY_DISPLAY_START_SHIFT   12
 
#define CIRRUS_SR_EXTENDED_MODE   7
 
#define CIRRUS_SR_EXTENDED_MODE_LFB_ENABLE   0xf0
 
#define CIRRUS_SR_EXTENDED_MODE_ENABLE_EXT   0x01
 
#define CIRRUS_SR_EXTENDED_MODE_32BPP   0x08
 
#define CIRRUS_HIDDEN_DAC_888COLOR   0xc5
 

Enumerations

enum  {
  VGA_CR_HTOTAL = 0x00 , VGA_CR_HORIZ_END = 0x01 , VGA_CR_HBLANK_START = 0x02 , VGA_CR_HBLANK_END = 0x03 ,
  VGA_CR_HORIZ_SYNC_PULSE_START = 0x04 , VGA_CR_HORIZ_SYNC_PULSE_END = 0x05 , VGA_CR_VERT_TOTAL = 0x06 , VGA_CR_OVERFLOW = 0x07 ,
  VGA_CR_BYTE_PANNING = 0x08 , VGA_CR_CELL_HEIGHT = 0x09 , VGA_CR_CURSOR_START = 0x0a , VGA_CR_CURSOR_END = 0x0b ,
  VGA_CR_START_ADDR_HIGH_REGISTER = 0x0c , VGA_CR_START_ADDR_LOW_REGISTER = 0x0d , VGA_CR_CURSOR_ADDR_HIGH = 0x0e , VGA_CR_CURSOR_ADDR_LOW = 0x0f ,
  VGA_CR_VSYNC_START = 0x10 , VGA_CR_VSYNC_END = 0x11 , VGA_CR_VDISPLAY_END = 0x12 , VGA_CR_PITCH = 0x13 ,
  VGA_CR_UNDERLINE_LOCATION = 0x14 , VGA_CR_VERTICAL_BLANK_START = 0x15 , VGA_CR_VERTICAL_BLANK_END = 0x16 , VGA_CR_MODE = 0x17 ,
  VGA_CR_LINE_COMPARE = 0x18
}
 
enum  { VGA_CR_CURSOR_START_DISABLE = (1 << 5) }
 
enum  {
  VGA_CR_MODE_NO_CGA = 0x01 , VGA_CR_MODE_NO_HERCULES = 0x02 , VGA_CR_MODE_ADDRESS_WRAP = 0x20 , VGA_CR_MODE_BYTE_MODE = 0x40 ,
  VGA_CR_MODE_TIMING_ENABLE = 0x80
}
 
enum  {
  VGA_SR_RESET = 0 , VGA_SR_CLOCKING_MODE = 1 , VGA_SR_MAP_MASK_REGISTER = 2 , VGA_SR_CHAR_MAP_SELECT = 3 ,
  VGA_SR_MEMORY_MODE = 4
}
 
enum  { VGA_SR_RESET_ASYNC = 1 , VGA_SR_RESET_SYNC = 2 }
 
enum  { VGA_SR_CLOCKING_MODE_8_DOT_CLOCK = 1 }
 
enum  { VGA_SR_MEMORY_MODE_NORMAL = 0 , VGA_SR_MEMORY_MODE_EXTERNAL_VIDEO_MEMORY = 2 , VGA_SR_MEMORY_MODE_SEQUENTIAL_ADDRESSING = 4 , VGA_SR_MEMORY_MODE_CHAIN4 = 8 }
 
enum  {
  VGA_GR_SET_RESET_PLANE = 0 , VGA_GR_SET_RESET_PLANE_ENABLE = 1 , VGA_GR_COLOR_COMPARE = 2 , VGA_GR_READ_MAP_REGISTER = 4 ,
  VGA_GR_MODE = 5 , VGA_GR_GR6 = 6 , VGA_GR_COLOR_COMPARE_DISABLE = 7 , VGA_GR_BITMASK = 8 ,
  VGA_GR_MAX
}
 
enum  { VGA_TEXT_TEXT_PLANE = 0 , VGA_TEXT_ATTR_PLANE = 1 , VGA_TEXT_FONT_PLANE = 2 }
 
enum  { VGA_GR_GR6_GRAPHICS_MODE = 1 , VGA_GR_GR6_MMAP_A0 = (1 << 2) , VGA_GR_GR6_MMAP_CGA = (3 << 2) }
 
enum  { VGA_GR_MODE_READ_MODE1 = 0x08 , VGA_GR_MODE_ODD_EVEN = 0x10 , VGA_GR_MODE_ODD_EVEN_SHIFT = 0x20 , VGA_GR_MODE_256_COLOR = 0x40 }
 

Functions

static void write_hidden_dac (uint8_t data)
 
static void cirrus_init_linear_fb (struct device *dev)
 
static void cirrus_init_text_mode (struct device *dev)
 
static void cirrus_init (struct device *dev)
 

Variables

static int width = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_XRES
 
static int height = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_YRES
 
static u32 addr = 0
 
static struct device_operations qemu_cirrus_graph_ops
 
static const struct pci_driver qemu_cirrus_driver __pci_driver
 

Macro Definition Documentation

◆ CIRRUS_CR_EXTENDED_DISPLAY

#define CIRRUS_CR_EXTENDED_DISPLAY   0x1b

Definition at line 155 of file cirrus.c.

◆ CIRRUS_CR_EXTENDED_DISPLAY_PITCH_MASK

#define CIRRUS_CR_EXTENDED_DISPLAY_PITCH_MASK   0x10

Definition at line 158 of file cirrus.c.

◆ CIRRUS_CR_EXTENDED_DISPLAY_PITCH_SHIFT

#define CIRRUS_CR_EXTENDED_DISPLAY_PITCH_SHIFT   4

Definition at line 159 of file cirrus.c.

◆ CIRRUS_CR_EXTENDED_DISPLAY_START_MASK1

#define CIRRUS_CR_EXTENDED_DISPLAY_START_MASK1   0x1

Definition at line 160 of file cirrus.c.

◆ CIRRUS_CR_EXTENDED_DISPLAY_START_MASK2

#define CIRRUS_CR_EXTENDED_DISPLAY_START_MASK2   0xc

Definition at line 162 of file cirrus.c.

◆ CIRRUS_CR_EXTENDED_DISPLAY_START_SHIFT1

#define CIRRUS_CR_EXTENDED_DISPLAY_START_SHIFT1   16

Definition at line 161 of file cirrus.c.

◆ CIRRUS_CR_EXTENDED_DISPLAY_START_SHIFT2

#define CIRRUS_CR_EXTENDED_DISPLAY_START_SHIFT2   15

Definition at line 163 of file cirrus.c.

◆ CIRRUS_CR_EXTENDED_OVERLAY

#define CIRRUS_CR_EXTENDED_OVERLAY   0x1d

Definition at line 156 of file cirrus.c.

◆ CIRRUS_CR_EXTENDED_OVERLAY_DISPLAY_START_MASK

#define CIRRUS_CR_EXTENDED_OVERLAY_DISPLAY_START_MASK   0x80

Definition at line 165 of file cirrus.c.

◆ CIRRUS_CR_EXTENDED_OVERLAY_DISPLAY_START_SHIFT

#define CIRRUS_CR_EXTENDED_OVERLAY_DISPLAY_START_SHIFT   12

Definition at line 166 of file cirrus.c.

◆ CIRRUS_HIDDEN_DAC_888COLOR

#define CIRRUS_HIDDEN_DAC_888COLOR   0xc5

Definition at line 171 of file cirrus.c.

◆ CIRRUS_SR_EXTENDED_MODE

#define CIRRUS_SR_EXTENDED_MODE   7

Definition at line 167 of file cirrus.c.

◆ CIRRUS_SR_EXTENDED_MODE_32BPP

#define CIRRUS_SR_EXTENDED_MODE_32BPP   0x08

Definition at line 170 of file cirrus.c.

◆ CIRRUS_SR_EXTENDED_MODE_ENABLE_EXT

#define CIRRUS_SR_EXTENDED_MODE_ENABLE_EXT   0x01

Definition at line 169 of file cirrus.c.

◆ CIRRUS_SR_EXTENDED_MODE_LFB_ENABLE

#define CIRRUS_SR_EXTENDED_MODE_LFB_ENABLE   0xf0

Definition at line 168 of file cirrus.c.

◆ VGA_CR_CELL_HEIGHT_DOUBLE_SCAN

#define VGA_CR_CELL_HEIGHT_DOUBLE_SCAN   0x80

Definition at line 75 of file cirrus.c.

◆ VGA_CR_CELL_HEIGHT_LINE_COMPARE_MASK

#define VGA_CR_CELL_HEIGHT_LINE_COMPARE_MASK   0x40

Definition at line 71 of file cirrus.c.

◆ VGA_CR_CELL_HEIGHT_LINE_COMPARE_SHIFT

#define VGA_CR_CELL_HEIGHT_LINE_COMPARE_SHIFT   3

Definition at line 72 of file cirrus.c.

◆ VGA_CR_CELL_HEIGHT_VERTICAL_BLANK_MASK

#define VGA_CR_CELL_HEIGHT_VERTICAL_BLANK_MASK   0x20

Definition at line 73 of file cirrus.c.

◆ VGA_CR_CELL_HEIGHT_VERTICAL_BLANK_SHIFT

#define VGA_CR_CELL_HEIGHT_VERTICAL_BLANK_SHIFT   4

Definition at line 74 of file cirrus.c.

◆ VGA_CR_OVERFLOW_HEIGHT1_MASK

#define VGA_CR_OVERFLOW_HEIGHT1_MASK   0x02

Definition at line 65 of file cirrus.c.

◆ VGA_CR_OVERFLOW_HEIGHT1_SHIFT

#define VGA_CR_OVERFLOW_HEIGHT1_SHIFT   7

Definition at line 64 of file cirrus.c.

◆ VGA_CR_OVERFLOW_HEIGHT2_MASK

#define VGA_CR_OVERFLOW_HEIGHT2_MASK   0xc0

Definition at line 67 of file cirrus.c.

◆ VGA_CR_OVERFLOW_HEIGHT2_SHIFT

#define VGA_CR_OVERFLOW_HEIGHT2_SHIFT   3

Definition at line 66 of file cirrus.c.

◆ VGA_CR_OVERFLOW_LINE_COMPARE_MASK

#define VGA_CR_OVERFLOW_LINE_COMPARE_MASK   0x10

Definition at line 69 of file cirrus.c.

◆ VGA_CR_OVERFLOW_LINE_COMPARE_SHIFT

#define VGA_CR_OVERFLOW_LINE_COMPARE_SHIFT   4

Definition at line 68 of file cirrus.c.

◆ VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END1_MASK

#define VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END1_MASK   0x02

Definition at line 50 of file cirrus.c.

◆ VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END1_SHIFT

#define VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END1_SHIFT   7

Definition at line 49 of file cirrus.c.

◆ VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END2_MASK

#define VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END2_MASK   0x40

Definition at line 52 of file cirrus.c.

◆ VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END2_SHIFT

#define VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END2_SHIFT   3

Definition at line 51 of file cirrus.c.

◆ VGA_CR_OVERFLOW_VERT_TOTAL1_MASK

#define VGA_CR_OVERFLOW_VERT_TOTAL1_MASK   0x01

Definition at line 55 of file cirrus.c.

◆ VGA_CR_OVERFLOW_VERT_TOTAL1_SHIFT

#define VGA_CR_OVERFLOW_VERT_TOTAL1_SHIFT   8

Definition at line 54 of file cirrus.c.

◆ VGA_CR_OVERFLOW_VERT_TOTAL2_MASK

#define VGA_CR_OVERFLOW_VERT_TOTAL2_MASK   0x20

Definition at line 57 of file cirrus.c.

◆ VGA_CR_OVERFLOW_VERT_TOTAL2_SHIFT

#define VGA_CR_OVERFLOW_VERT_TOTAL2_SHIFT   4

Definition at line 56 of file cirrus.c.

◆ VGA_CR_OVERFLOW_VSYNC_START1_MASK

#define VGA_CR_OVERFLOW_VSYNC_START1_MASK   0x04

Definition at line 60 of file cirrus.c.

◆ VGA_CR_OVERFLOW_VSYNC_START1_SHIFT

#define VGA_CR_OVERFLOW_VSYNC_START1_SHIFT   6

Definition at line 59 of file cirrus.c.

◆ VGA_CR_OVERFLOW_VSYNC_START2_MASK

#define VGA_CR_OVERFLOW_VSYNC_START2_MASK   0x80

Definition at line 62 of file cirrus.c.

◆ VGA_CR_OVERFLOW_VSYNC_START2_SHIFT

#define VGA_CR_OVERFLOW_VSYNC_START2_SHIFT   2

Definition at line 61 of file cirrus.c.

◆ VGA_CR_PITCH_DIVISOR

#define VGA_CR_PITCH_DIVISOR   8

Definition at line 81 of file cirrus.c.

◆ VGA_CR_WIDTH_DIVISOR

#define VGA_CR_WIDTH_DIVISOR   8

Definition at line 47 of file cirrus.c.

◆ VGA_IO_MISC_COLOR

#define VGA_IO_MISC_COLOR   0x01

Definition at line 45 of file cirrus.c.

Enumeration Type Documentation

◆ anonymous enum

anonymous enum
Enumerator
VGA_CR_HTOTAL 
VGA_CR_HORIZ_END 
VGA_CR_HBLANK_START 
VGA_CR_HBLANK_END 
VGA_CR_HORIZ_SYNC_PULSE_START 
VGA_CR_HORIZ_SYNC_PULSE_END 
VGA_CR_VERT_TOTAL 
VGA_CR_OVERFLOW 
VGA_CR_BYTE_PANNING 
VGA_CR_CELL_HEIGHT 
VGA_CR_CURSOR_START 
VGA_CR_CURSOR_END 
VGA_CR_START_ADDR_HIGH_REGISTER 
VGA_CR_START_ADDR_LOW_REGISTER 
VGA_CR_CURSOR_ADDR_HIGH 
VGA_CR_CURSOR_ADDR_LOW 
VGA_CR_VSYNC_START 
VGA_CR_VSYNC_END 
VGA_CR_VDISPLAY_END 
VGA_CR_PITCH 
VGA_CR_UNDERLINE_LOCATION 
VGA_CR_VERTICAL_BLANK_START 
VGA_CR_VERTICAL_BLANK_END 
VGA_CR_MODE 
VGA_CR_LINE_COMPARE 

Definition at line 16 of file cirrus.c.

◆ anonymous enum

anonymous enum
Enumerator
VGA_CR_CURSOR_START_DISABLE 

Definition at line 76 of file cirrus.c.

◆ anonymous enum

anonymous enum
Enumerator
VGA_CR_MODE_NO_CGA 
VGA_CR_MODE_NO_HERCULES 
VGA_CR_MODE_ADDRESS_WRAP 
VGA_CR_MODE_BYTE_MODE 
VGA_CR_MODE_TIMING_ENABLE 

Definition at line 83 of file cirrus.c.

◆ anonymous enum

anonymous enum
Enumerator
VGA_SR_RESET 
VGA_SR_CLOCKING_MODE 
VGA_SR_MAP_MASK_REGISTER 
VGA_SR_CHAR_MAP_SELECT 
VGA_SR_MEMORY_MODE 

Definition at line 92 of file cirrus.c.

◆ anonymous enum

anonymous enum
Enumerator
VGA_SR_RESET_ASYNC 
VGA_SR_RESET_SYNC 

Definition at line 101 of file cirrus.c.

◆ anonymous enum

anonymous enum
Enumerator
VGA_SR_CLOCKING_MODE_8_DOT_CLOCK 

Definition at line 107 of file cirrus.c.

◆ anonymous enum

anonymous enum
Enumerator
VGA_SR_MEMORY_MODE_NORMAL 
VGA_SR_MEMORY_MODE_EXTERNAL_VIDEO_MEMORY 
VGA_SR_MEMORY_MODE_SEQUENTIAL_ADDRESSING 
VGA_SR_MEMORY_MODE_CHAIN4 

Definition at line 112 of file cirrus.c.

◆ anonymous enum

anonymous enum
Enumerator
VGA_GR_SET_RESET_PLANE 
VGA_GR_SET_RESET_PLANE_ENABLE 
VGA_GR_COLOR_COMPARE 
VGA_GR_READ_MAP_REGISTER 
VGA_GR_MODE 
VGA_GR_GR6 
VGA_GR_COLOR_COMPARE_DISABLE 
VGA_GR_BITMASK 
VGA_GR_MAX 

Definition at line 120 of file cirrus.c.

◆ anonymous enum

anonymous enum
Enumerator
VGA_TEXT_TEXT_PLANE 
VGA_TEXT_ATTR_PLANE 
VGA_TEXT_FONT_PLANE 

Definition at line 133 of file cirrus.c.

◆ anonymous enum

anonymous enum
Enumerator
VGA_GR_GR6_GRAPHICS_MODE 
VGA_GR_GR6_MMAP_A0 
VGA_GR_GR6_MMAP_CGA 

Definition at line 140 of file cirrus.c.

◆ anonymous enum

anonymous enum
Enumerator
VGA_GR_MODE_READ_MODE1 
VGA_GR_MODE_ODD_EVEN 
VGA_GR_MODE_ODD_EVEN_SHIFT 
VGA_GR_MODE_256_COLOR 

Definition at line 147 of file cirrus.c.

Function Documentation

◆ cirrus_init()

static void cirrus_init ( struct device dev)
static

Definition at line 311 of file cirrus.c.

◆ cirrus_init_linear_fb()

static void cirrus_init_linear_fb ( struct device dev)
static

Definition at line 184 of file cirrus.c.

References addr, BIOS_DEBUG, CIRRUS_CR_EXTENDED_DISPLAY, CIRRUS_CR_EXTENDED_DISPLAY_PITCH_MASK, CIRRUS_CR_EXTENDED_DISPLAY_PITCH_SHIFT, CIRRUS_CR_EXTENDED_DISPLAY_START_MASK1, CIRRUS_CR_EXTENDED_DISPLAY_START_MASK2, CIRRUS_CR_EXTENDED_OVERLAY, CIRRUS_CR_EXTENDED_OVERLAY_DISPLAY_START_MASK, CIRRUS_HIDDEN_DAC_888COLOR, CIRRUS_SR_EXTENDED_MODE, CIRRUS_SR_EXTENDED_MODE_32BPP, CIRRUS_SR_EXTENDED_MODE_ENABLE_EXT, CIRRUS_SR_EXTENDED_MODE_LFB_ENABLE, fb_add_framebuffer_info(), height, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_MEM_ATTR_MASK, pci_read_config32(), printk, VGA_CR_CELL_HEIGHT, VGA_CR_CELL_HEIGHT_LINE_COMPARE_MASK, VGA_CR_CELL_HEIGHT_LINE_COMPARE_SHIFT, VGA_CR_CELL_HEIGHT_VERTICAL_BLANK_MASK, VGA_CR_CELL_HEIGHT_VERTICAL_BLANK_SHIFT, VGA_CR_HBLANK_END, VGA_CR_HBLANK_START, VGA_CR_HORIZ_END, VGA_CR_HORIZ_SYNC_PULSE_END, VGA_CR_HORIZ_SYNC_PULSE_START, VGA_CR_HTOTAL, VGA_CR_LINE_COMPARE, VGA_CR_MODE, VGA_CR_MODE_BYTE_MODE, VGA_CR_MODE_NO_CGA, VGA_CR_MODE_NO_HERCULES, VGA_CR_MODE_TIMING_ENABLE, VGA_CR_OVERFLOW, VGA_CR_OVERFLOW_LINE_COMPARE_MASK, VGA_CR_OVERFLOW_LINE_COMPARE_SHIFT, VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END1_MASK, VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END1_SHIFT, VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END2_MASK, VGA_CR_OVERFLOW_VERT_DISPLAY_ENABLE_END2_SHIFT, VGA_CR_OVERFLOW_VERT_TOTAL1_MASK, VGA_CR_OVERFLOW_VERT_TOTAL1_SHIFT, VGA_CR_OVERFLOW_VERT_TOTAL2_MASK, VGA_CR_OVERFLOW_VERT_TOTAL2_SHIFT, VGA_CR_OVERFLOW_VSYNC_START1_MASK, VGA_CR_OVERFLOW_VSYNC_START1_SHIFT, VGA_CR_OVERFLOW_VSYNC_START2_MASK, VGA_CR_OVERFLOW_VSYNC_START2_SHIFT, VGA_CR_PITCH, VGA_CR_PITCH_DIVISOR, vga_cr_read(), VGA_CR_START_ADDR_HIGH_REGISTER, VGA_CR_START_ADDR_LOW_REGISTER, VGA_CR_VDISPLAY_END, VGA_CR_VERT_TOTAL, VGA_CR_VERTICAL_BLANK_END, VGA_CR_VERTICAL_BLANK_START, VGA_CR_VSYNC_END, VGA_CR_VSYNC_START, VGA_CR_WIDTH_DIVISOR, vga_cr_write(), VGA_GR_GR6, VGA_GR_GR6_GRAPHICS_MODE, VGA_GR_MODE, VGA_GR_MODE_256_COLOR, VGA_GR_MODE_READ_MODE1, vga_gr_write(), VGA_IO_MISC_COLOR, vga_misc_write(), vga_palette_disable(), VGA_SR_CLOCKING_MODE, VGA_SR_CLOCKING_MODE_8_DOT_CLOCK, VGA_SR_MAP_MASK_REGISTER, VGA_SR_MEMORY_MODE, VGA_SR_MEMORY_MODE_NORMAL, vga_sr_write(), VGA_TEXT_ATTR_PLANE, VGA_TEXT_TEXT_PLANE, width, and write_hidden_dac().

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◆ cirrus_init_text_mode()

static void cirrus_init_text_mode ( struct device dev)
static

Definition at line 305 of file cirrus.c.

References vga_misc_write(), and vga_textmode_init().

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◆ write_hidden_dac()

static void write_hidden_dac ( uint8_t  data)
static

Definition at line 174 of file cirrus.c.

References inb(), and outb().

Referenced by cirrus_init_linear_fb().

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Variable Documentation

◆ __pci_driver

const struct pci_driver qemu_cirrus_driver __pci_driver
static
Initial value:
= {
.vendor = 0x1013,
.device = 0x00b8,
}
static struct device_operations qemu_cirrus_graph_ops
Definition: cirrus.c:319

Definition at line 311 of file cirrus.c.

◆ addr

u32 addr = 0
static

Definition at line 14 of file cirrus.c.

Referenced by __asan_loadN(), __asan_loadN_noabort(), __asan_poison_stack_memory(), __asan_report_load_n_noabort(), __asan_report_store_n_noabort(), __asan_storeN(), __asan_storeN_noabort(), __asan_unpoison_stack_memory(), __ec_read(), __ec_write(), acpi_create_einj(), acpi_create_hpet(), acpi_create_ipmi(), acpi_create_madt_ioapic(), acpi_fill_hest(), acpi_fill_madt(), acpigen_soc_get_dw0_in_local5(), acpigen_soc_get_gpio_val(), acpigen_soc_set_gpio_val(), acpigen_write_empty_PTC(), acpigen_write_register(), acpigen_write_register_resource(), add_mmio_resource(), am335x_wait_for_reg(), asan_mem_to_shadow(), asan_report(), aspeed_early_config(), assert_correct_ttb_mapping(), ast_backup_fw(), ast_set_start_address_crt1(), at24rf08c_read_byte(), azalia_codec_init(), bh720_read_pcr(), bh720_rmw_pcr(), bh720_write_pcr(), biosemu_dev_translate_address(), buf_read(), buf_write(), calibrate_receive_enable(), cbmem_top_chipset(), check_idle(), check_memory_region(), check_memory_region_inline(), check_pirq_routing_table(), check_testing_type2(), cirrus_init_linear_fb(), clflush(), clock_set_mshci(), clrbits32(), cmos_read(), cmos_write(), cmos_write_inner(), compute_ip_checksum(), copy_pirq_routing_table(), cper_new_ia32x64_context_msr(), cr50_i2c_read(), cr50_i2c_tis_recv(), cr50_i2c_write(), crb_wait_for_reg32(), crport_write(), CS_change(), dbgp_bulk_read(), dbgp_bulk_write(), dbgp_control_msg(), dcache_clean_by_mva(), dcache_clean_invalidate_by_mva(), dcache_invalidate_by_mva(), dcache_op_mva(), dcache_op_va(), ddr3_mirror_mrreg(), ddr3_read_io_init(), ddr_phy_pll_setting(), decr_coarse_low(), dev_find_slot_on_smbus(), disable_device(), disable_func(), disable_xhci_lfps_pm(), dma_read(), do_ram_command(), dqsosc_auto(), dram_odt_stretch(), dramc_cmd_bus_training(), dramc_rx_dqs_gating_cal(), dramc_zq_calibration(), dt_init_reserved_memory_node(), dt_platform_fixup(), dump(), dump_stack(), dump_state(), ec_clr_bit(), ec_cmd_90_read(), ec_cmd_91_write(), ec_idx_read(), ec_idx_write(), ec_mem_read(), ec_mem_write(), ec_oem_read(), ec_oem_write(), ec_read(), ec_set_bit(), ec_write(), ecam0_pci_enable_msix(), enable_device(), enable_func(), fast_spi_flash_ctrlr_reg_read(), fast_spi_flash_ctrlr_reg_write(), fast_spi_flash_read(), fast_spi_flash_write(), fill_pattern0(), fill_pattern1(), fill_pattern5(), find_dqs_edge_lowhigh(), find_dqs_high(), find_dqs_low(), find_first_bad_addr(), find_preamble(), fine_search_dqs_high(), flush_cache(), fsp_next_hob(), get_580(), get_etalon(), get_etalon2(), get_pte(), get_shadow_bug_type(), get_spd(), get_srat_memory_entries(), get_xfer_len(), google_chromeec_i2c_xfer(), gpi_firmware_load(), gpio_tlmm_config_get(), handle_misaligned(), hda_codec_init(), hdmi_phy_i2c_write(), hob_header_to_extension_hob(), hob_header_to_struct(), i2c_send(), ich_hwseq_read(), ich_hwseq_set_addr(), ich_hwseq_wait_for_cycle_complete(), ich_hwseq_write(), iic_tpm_read(), iic_tpm_write(), iic_tpm_write_generic(), iic_tpm_write_long(), in16le(), in32le(), init_dram_ddr3(), insb(), insl(), insw(), is_car_addr(), kempld_i2c_process(), kempld_read8(), kempld_write8(), lb_table_init(), ledc_read(), lpc_enable_sio_decode(), lpc_read(), lpc_write(), lpss_clk_update(), lpss_is_controller_in_reset(), lpss_reset_release(), lumpy_smbios_type41_irq(), mainboard_enable(), mainboard_smi_sleep(), map_spi_rom(), mem_access_word(), mem_ptr(), memory_is_poisoned(), memory_is_poisoned_1(), memory_is_poisoned_16(), memory_is_poisoned_2_4_8(), memory_is_poisoned_n(), mmio_andthenor32(), msdc_poll_timeout(), msdc_wait_done(), mt6315_init_setting(), mt6358_init_setting(), mt6358_lp_setting(), mt6366_init_scp_voltage(), mt6366_init_setting(), mt6366_lp_setting(), mt6391_configure_ldo(), mt_mem_test(), mtk_dp_mask(), mtk_dp_read(), mtk_dp_write(), mtk_dp_write_byte(), mtk_i2c_transfer(), my_inb(), my_inl(), my_inw(), my_outb(), my_outl(), my_outw(), my_rdb(), my_rdl(), my_rdw(), my_wrb(), my_wrl(), my_wrw(), new_pci_sdhci_controller(), nor_read(), nor_write(), out16le(), out32le(), outsb(), outsl(), outsw(), p_inb(), p_inl(), p_inw(), p_outb(), p_outl(), p_outw(), pch_iobp_exec(), pci_cfg_read(), pci_cfg_write(), pci_io_encode_addr(), pci_io_read_config16(), pci_io_read_config32(), pci_io_read_config8(), pci_io_write_config16(), pci_io_write_config32(), pci_io_write_config8(), perform_raminit(), perform_write_training(), pirq_route_irqs(), pmc_set_disb(), pmic_efuse_setting(), pmic_init_scp_voltage(), pmic_init_setting(), pmic_lp_setting(), pmic_protect_key_setting(), pmic_read(), pmif_send_cmd(), pmm_test(), postcar_frame_add_mtrr(), postcar_var_mtrr_set(), probe_mb(), prog_rcomp(), push_stack(), pwrap_read(), pwrap_read_nochk(), pwrap_wacs2(), pwrap_write(), pwrap_write_nochk(), qup_common_init(), qup_i2c_read_fifo(), qup_i2c_write_fifo(), ram_bitset_nodie(), ram_check_noprint_nodie(), raminit(), rcven(), rdb(), rdl(), rdw(), read128(), read16(), read16p(), read32(), read32p(), read64(), read64p(), read8(), read8p(), read_1d0(), read_500(), read_io(), read_phys(), read_pmbase16(), read_pmbase32(), read_pmbase8(), read_scom(), read_scom_for_chiplet(), read_scom_indirect(), read_spd(), restore_timings(), rk_edp_dpcd_read(), rk_edp_dpcd_write(), rmw_1d0(), rmw_500(), rtc_read(), rtc_write(), run_bios(), sample_strobes(), sampledqs(), sanity_check(), sata_enable_ahci_mmap(), sch5545_emi_ec_read16(), sch5545_emi_ec_read32(), sch5545_emi_ec_read32_bulk(), sch5545_emi_ec_read8(), sch5545_emi_ec_write16(), sch5545_emi_ec_write32(), sch5545_emi_ec_write32_bulk(), sch5545_emi_ec_write8(), sch5545_emi_set_ec_addr(), scom_and(), scom_and_for_chiplet(), scom_and_or(), scom_and_or_for_chiplet(), scom_or(), scom_or_for_chiplet(), sdram_dradrb(), sdram_patch(), sdram_patch_bootrom(), send_jedec_cmd(), set_mmc_clk(), set_mpll_2500(), set_selph_gating_value(), set_sfpaddr(), set_xhci_lfps_sampling_offtime(), setbits32(), smbus_i2c_block_write(), smbus_read_byte(), smbus_read_spd(), smbus_write_byte(), smp_write_floating_table(), smp_write_floating_table_physaddr(), soc_get_ioapic_info(), spi_flash_addr(), system76_ec_read(), system76_ec_write(), tas5825m_write_at(), tas5825m_write_block_at(), tegra_dc_dpaux_read(), tegra_dc_dpaux_read_chunk(), tegra_dc_dpaux_write_chunk(), tegra_dc_i2c_aux_read(), tegra_dpaux_readl(), tegra_dpaux_writel(), tegra_sor_readl(), tegra_sor_writel(), test_dimm(), test_pattern(), tpm_vendor_probe(), trustzone_init(), var_mtrr_set(), var_mtrr_set_with_cb(), verify_copy_pirq_routing_table(), wrb(), write16(), write16p(), write32(), write32p(), write64(), write64p(), write8(), write8p(), write_1d0(), write_500(), write_io(), write_phys(), write_pirq_routing_table(), write_pmbase16(), write_pmbase32(), write_pmbase8(), write_scom(), write_scom_for_chiplet(), write_scom_indirect(), write_smp_table(), write_training_test(), writebits(), wrl(), wrw(), x86_exception(), and x86emuOp_xlat().

◆ height

int height = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_YRES
static

Definition at line 13 of file cirrus.c.

Referenced by cirrus_init_linear_fb().

◆ qemu_cirrus_graph_ops

struct device_operations qemu_cirrus_graph_ops
static
Initial value:
= {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = cirrus_init,
}
static void cirrus_init(struct device *dev)
Definition: cirrus.c:311
void pci_dev_enable_resources(struct device *dev)
Definition: pci_device.c:721
void pci_dev_read_resources(struct device *dev)
Definition: pci_device.c:534
void pci_dev_set_resources(struct device *dev)
Definition: pci_device.c:691

Definition at line 311 of file cirrus.c.

◆ width

int width = CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_XRES
static

Definition at line 12 of file cirrus.c.

Referenced by cirrus_init_linear_fb().