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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <arch/io.h>
#include <soc/gpio.h>
#include <soc/pm.h>
#include <device/mmio.h>
#include <soc/iomap.h>
Go to the source code of this file.
Macros | |
#define | SUSPEND_CYCLE 1 |
#define | RESUME_CYCLE 0 |
#define | LPC_FAMILY_NUMBER(gpio_pad) (gpio_pad / MAX_FAMILY_PAD_GPIO_NO) |
#define | LPC_INTERNAL_PAD_NUM(gpio_pad) (gpio_pad % MAX_FAMILY_PAD_GPIO_NO) |
#define | LPC_GPIO_OFFSET(gpio_pad) |
#define | LPC_AD2_MMIO_OFFSET LPC_GPIO_OFFSET(45) |
#define | LPC_CLKRUN_MMIO_OFFSET LPC_GPIO_OFFSET(46) |
#define | LPC_AD0_MMIO_OFFSET LPC_GPIO_OFFSET(47) |
#define | LPC_FRAME_MMIO_OFFSET LPC_GPIO_OFFSET(48) |
#define | LPC_AD3_MMIO_OFFSET LPC_GPIO_OFFSET(50) |
#define | LPC_AD1_MMIO_OFFSET LPC_GPIO_OFFSET(52) |
#define | PAD_CFG0_NATIVE(mode, term, inv_rx_tx) |
#define | PAD_CFG0_NATIVE_PU20K(mode) PAD_CFG0_NATIVE(mode, 9, 0) /* PU 20K */ |
#define | PAD_CFG0_NATIVE_PD20K(mode) PAD_CFG0_NATIVE(mode, 1, 0) /* PD 20K */ |
#define | PAD_CFG0_NATIVE_M1 PAD_CFG0_NATIVE(1, 0, 0) /* no pull */ |
Functions | |
static void | lpc_gpio_config (u32 cycle) |
void | lpc_set_low_power (void) |
void | lpc_init (void) |
#define LPC_AD0_MMIO_OFFSET LPC_GPIO_OFFSET(47) |
Definition at line 19 of file lpc_init.c.
#define LPC_AD1_MMIO_OFFSET LPC_GPIO_OFFSET(52) |
Definition at line 22 of file lpc_init.c.
#define LPC_AD2_MMIO_OFFSET LPC_GPIO_OFFSET(45) |
Definition at line 17 of file lpc_init.c.
#define LPC_AD3_MMIO_OFFSET LPC_GPIO_OFFSET(50) |
Definition at line 21 of file lpc_init.c.
#define LPC_CLKRUN_MMIO_OFFSET LPC_GPIO_OFFSET(46) |
Definition at line 18 of file lpc_init.c.
#define LPC_FAMILY_NUMBER | ( | gpio_pad | ) | (gpio_pad / MAX_FAMILY_PAD_GPIO_NO) |
Definition at line 11 of file lpc_init.c.
#define LPC_FRAME_MMIO_OFFSET LPC_GPIO_OFFSET(48) |
Definition at line 20 of file lpc_init.c.
#define LPC_GPIO_OFFSET | ( | gpio_pad | ) |
Definition at line 13 of file lpc_init.c.
#define LPC_INTERNAL_PAD_NUM | ( | gpio_pad | ) | (gpio_pad % MAX_FAMILY_PAD_GPIO_NO) |
Definition at line 12 of file lpc_init.c.
#define PAD_CFG0_NATIVE | ( | mode, | |
term, | |||
inv_rx_tx | |||
) |
Definition at line 25 of file lpc_init.c.
#define PAD_CFG0_NATIVE_M1 PAD_CFG0_NATIVE(1, 0, 0) /* no pull */ |
Definition at line 31 of file lpc_init.c.
#define PAD_CFG0_NATIVE_PD20K | ( | mode | ) | PAD_CFG0_NATIVE(mode, 1, 0) /* PD 20K */ |
Definition at line 30 of file lpc_init.c.
#define PAD_CFG0_NATIVE_PU20K | ( | mode | ) | PAD_CFG0_NATIVE(mode, 9, 0) /* PU 20K */ |
Definition at line 29 of file lpc_init.c.
#define RESUME_CYCLE 0 |
Definition at line 10 of file lpc_init.c.
#define SUSPEND_CYCLE 1 |
Definition at line 9 of file lpc_init.c.
Definition at line 37 of file lpc_init.c.
References COMMUNITY_GPSOUTHEAST_BASE, LPC_AD0_MMIO_OFFSET, LPC_AD1_MMIO_OFFSET, LPC_AD2_MMIO_OFFSET, LPC_AD3_MMIO_OFFSET, LPC_CLKRUN_MMIO_OFFSET, LPC_FRAME_MMIO_OFFSET, PAD_CFG0_NATIVE_M1, PAD_CFG0_NATIVE_PD20K, PAD_CFG0_NATIVE_PU20K, SUSPEND_CYCLE, and write32().
Referenced by lpc_init(), and lpc_set_low_power().
Definition at line 90 of file lpc_init.c.
References ACPI_BASE_ADDRESS, ACPI_S3, ACPI_S5, inl(), inw(), lpc_gpio_config(), PM1_CNT, PM1_STS, RESUME_CYCLE, and WAK_STS.
Definition at line 82 of file lpc_init.c.
References lpc_gpio_config(), and SUSPEND_CYCLE.
Referenced by mainboard_smi_sleep().