9 #define SUSPEND_CYCLE 1
10 #define RESUME_CYCLE 0
11 #define LPC_FAMILY_NUMBER(gpio_pad) (gpio_pad / MAX_FAMILY_PAD_GPIO_NO)
12 #define LPC_INTERNAL_PAD_NUM(gpio_pad) (gpio_pad % MAX_FAMILY_PAD_GPIO_NO)
13 #define LPC_GPIO_OFFSET(gpio_pad) (FAMILY_PAD_REGS_OFF \
14 + (FAMILY_PAD_REGS_SIZE * LPC_FAMILY_NUMBER(gpio_pad) \
15 + (GPIO_REGS_SIZE * LPC_INTERNAL_PAD_NUM(gpio_pad))))
17 #define LPC_AD2_MMIO_OFFSET LPC_GPIO_OFFSET(45)
18 #define LPC_CLKRUN_MMIO_OFFSET LPC_GPIO_OFFSET(46)
19 #define LPC_AD0_MMIO_OFFSET LPC_GPIO_OFFSET(47)
20 #define LPC_FRAME_MMIO_OFFSET LPC_GPIO_OFFSET(48)
21 #define LPC_AD3_MMIO_OFFSET LPC_GPIO_OFFSET(50)
22 #define LPC_AD1_MMIO_OFFSET LPC_GPIO_OFFSET(52)
25 #define PAD_CFG0_NATIVE(mode, term, inv_rx_tx) (PAD_GPIO_DISABLE \
27 | PAD_MODE_SELECTION(mode) | PAD_PULL(term))
29 #define PAD_CFG0_NATIVE_PU20K(mode) PAD_CFG0_NATIVE(mode, 9, 0)
30 #define PAD_CFG0_NATIVE_PD20K(mode) PAD_CFG0_NATIVE(mode, 1, 0)
31 #define PAD_CFG0_NATIVE_M1 PAD_CFG0_NATIVE(1, 0, 0)
104 slp_type = acpi_sleep_from_pm1(pm1_cnt);
static void write32(void *addr, uint32_t val)
#define ACPI_BASE_ADDRESS
#define PAD_CFG0_NATIVE_M1
static void lpc_gpio_config(u32 cycle)
#define LPC_AD1_MMIO_OFFSET
#define LPC_AD2_MMIO_OFFSET
#define PAD_CFG0_NATIVE_PD20K(mode)
#define PAD_CFG0_NATIVE_PU20K(mode)
#define LPC_CLKRUN_MMIO_OFFSET
void lpc_set_low_power(void)
#define LPC_FRAME_MMIO_OFFSET
#define LPC_AD0_MMIO_OFFSET
#define LPC_AD3_MMIO_OFFSET
#define COMMUNITY_GPSOUTHEAST_BASE