5 #ifndef AMD_SABRINA_SOUTHBRIDGE_H
6 #define AMD_SABRINA_SOUTHBRIDGE_H
11 #define PM_ISACONTROL 0x04
12 #define ABCLKGATEEN BIT(16)
13 #define PM_PCI_CTRL 0x08
14 #define FORCE_SLPSTATE_RETRY BIT(25)
15 #define PWR_RESET_CFG 0x10
16 #define TOGGLE_ALL_PWR_GOOD (1 << 1)
17 #define PM_SERIRQ_CONF 0x54
18 #define PM_SERIRQ_NUM_BITS_17 0x0000
19 #define PM_SERIRQ_NUM_BITS_18 0x0004
20 #define PM_SERIRQ_NUM_BITS_19 0x0008
21 #define PM_SERIRQ_NUM_BITS_20 0x000c
22 #define PM_SERIRQ_NUM_BITS_21 0x0010
23 #define PM_SERIRQ_NUM_BITS_22 0x0014
24 #define PM_SERIRQ_NUM_BITS_23 0x0018
25 #define PM_SERIRQ_NUM_BITS_24 0x001c
26 #define PM_SERIRQ_MODE BIT(6)
27 #define PM_SERIRQ_ENABLE BIT(7)
28 #define PM_EVT_BLK 0x60
29 #define WAK_STS BIT(15)
30 #define PCIEXPWAK_STS BIT(14)
31 #define RTC_STS BIT(10)
32 #define PWRBTN_STS BIT(8)
33 #define GBL_STS BIT(5)
35 #define TIMER_STS BIT(0)
36 #define PCIEXPWAK_DIS BIT(14)
37 #define RTC_EN BIT(10)
38 #define PWRBTN_EN BIT(8)
40 #define TIMER_STS BIT(0)
41 #define PM1_CNT_BLK 0x62
42 #define PM_TMR_BLK 0x64
43 #define PM_GPE0_BLK 0x68
44 #define PM_ACPI_SMI_CMD 0x6a
45 #define PM_ACPI_CONF 0x74
46 #define PM_ACPI_DECODE_STD BIT(0)
47 #define PM_ACPI_GLOBAL_EN BIT(1)
48 #define PM_ACPI_RTC_EN_EN BIT(2)
49 #define PM_ACPI_SLPBTN_EN_EN BIT(3)
50 #define PM_ACPI_TIMER_EN_EN BIT(4)
51 #define PM_ACPI_MASK_ARB_DIS BIT(6)
52 #define PM_ACPI_BIOS_RLS BIT(7)
53 #define PM_ACPI_PWRBTNEN_EN BIT(8)
54 #define PM_ACPI_REDUCED_HW_EN BIT(9)
55 #define PM_ACPI_S5_LPC_PIN_MODE_SEL BIT(10)
56 #define PM_ACPI_S5_LPC_PIN_MODE BIT(11)
57 #define PM_ACPI_LPC_RST_DIS BIT(12)
58 #define PM_ACPI_SEL_PWRGD_PAD BIT(13)
59 #define PM_ACPI_SEL_SMU_THERMTRIP BIT(14)
60 #define PM_ACPI_SW_S5PWRMUX_OVRD_N BIT(15)
61 #define PM_ACPI_SW_S5PWRMUX BIT(16)
62 #define PM_ACPI_EN_SHUTDOWN_MSG BIT(17)
63 #define PM_ACPI_EN_SYNC_FLOOD BIT(18)
64 #define PM_ACPI_FORCE_SPIUSEPIN_0 BIT(19)
65 #define PM_ACPI_EN_DF_INTRWAKE BIT(20)
66 #define PM_ACPI_MASK_USB_S5_RST BIT(21)
67 #define PM_ACPI_USE_RSMU_RESET BIT(22)
68 #define PM_ACPI_RST_USB_S5 BIT(23)
69 #define PM_ACPI_BLOCK_PCIE_PME BIT(24)
70 #define PM_ACPI_PCIE_WAK_MASK BIT(25)
71 #define PM_ACPI_PCIE_WAK_INTR_DIS BIT(26)
72 #define PM_ACPI_WAKE_AS_GEVENT BIT(27)
73 #define PM_ACPI_NB_PME_GEVENT BIT(28)
74 #define PM_ACPI_RTC_WAKE_EN BIT(29)
75 #define PM_ACPI_USE_GATED_ALINK_CLK BIT(30)
76 #define PM_ACPI_DELAY_GPP_OFF_TIME BIT(31)
77 #define PM_SPI_PAD_PU_PD 0x90
78 #define PM_LPC_GATING 0xec
79 #define PM_LPC_AB_NO_BYPASS_EN BIT(2)
80 #define PM_LPC_A20_EN BIT(1)
81 #define PM_LPC_ENABLE BIT(0)
85 #define TOTAL_BITS(a) (8 * sizeof(a))
87 #define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20)
90 #define GPP_CLK_CNTRL 0x00
91 #define GPP_CLK0_REQ_SHIFT 0
92 #define GPP_CLK1_REQ_SHIFT 2
93 #define GPP_CLK4_REQ_SHIFT 4
94 #define GPP_CLK2_REQ_SHIFT 6
95 #define GPP_CLK3_REQ_SHIFT 8
96 #define GPP_CLK5_REQ_SHIFT 10
97 #define GPP_CLK6_REQ_SHIFT 12
98 #define GPP_CLK_OUTPUT_COUNT 7
99 #define GPP_CLK_REQ_MASK(clk_shift) (0x3 << (clk_shift))
100 #define GPP_CLK_REQ_ON(clk_shift) (0x3 << (clk_shift))
101 #define GPP_CLK_REQ_EXT(clk_shift) (0x1 << (clk_shift))
102 #define GPP_CLK_REQ_OFF(clk_shift) (0x0 << (clk_shift))
104 #define MISC_CLKGATEDCNTL 0x2c
105 #define ALINKCLK_GATEOFFEN BIT(16)
106 #define BLINKCLK_GATEOFFEN BIT(17)
107 #define XTAL_PAD_S3_TURNOFF_EN BIT(20)
108 #define XTAL_PAD_S5_TURNOFF_EN BIT(21)
109 #define MISC_CGPLL_CONFIGURATION0 0x30
110 #define USB_PHY_CMCLK_S3_DIS BIT(8)
111 #define USB_PHY_CMCLK_S0I3_DIS BIT(9)
112 #define USB_PHY_CMCLK_S5_DIS BIT(10)
113 #define MISC_CLK_CNTL0 0x40
114 #define BP_X48M0_S0I3_DIS BIT(4)
115 #define BP_X48M0_OUTPUT_EN BIT(2)
void fch_init(void *chip_info)
void enable_aoac_devices(void)
void fch_final(void *chip_info)
void wait_for_aoac_enabled(unsigned int dev)
void fch_early_init(void)