coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
Macros | Functions
southbridge.h File Reference
#include <soc/iomap.h>
Include dependency graph for southbridge.h:

Go to the source code of this file.

Macros

#define PM_ISACONTROL   0x04
 
#define ABCLKGATEEN   BIT(16)
 
#define PM_PCI_CTRL   0x08
 
#define FORCE_SLPSTATE_RETRY   BIT(25)
 
#define PWR_RESET_CFG   0x10
 
#define TOGGLE_ALL_PWR_GOOD   (1 << 1)
 
#define PM_SERIRQ_CONF   0x54
 
#define PM_SERIRQ_NUM_BITS_17   0x0000
 
#define PM_SERIRQ_NUM_BITS_18   0x0004
 
#define PM_SERIRQ_NUM_BITS_19   0x0008
 
#define PM_SERIRQ_NUM_BITS_20   0x000c
 
#define PM_SERIRQ_NUM_BITS_21   0x0010
 
#define PM_SERIRQ_NUM_BITS_22   0x0014
 
#define PM_SERIRQ_NUM_BITS_23   0x0018
 
#define PM_SERIRQ_NUM_BITS_24   0x001c
 
#define PM_SERIRQ_MODE   BIT(6)
 
#define PM_SERIRQ_ENABLE   BIT(7)
 
#define PM_EVT_BLK   0x60
 
#define WAK_STS   BIT(15) /*AcpiPmEvtBlkx00 Pm1Status */
 
#define PCIEXPWAK_STS   BIT(14)
 
#define RTC_STS   BIT(10)
 
#define PWRBTN_STS   BIT(8)
 
#define GBL_STS   BIT(5)
 
#define BM_STS   BIT(4)
 
#define TIMER_STS   BIT(0)
 
#define PCIEXPWAK_DIS   BIT(14) /*AcpiPmEvtBlkx02 Pm1Enable */
 
#define RTC_EN   BIT(10)
 
#define PWRBTN_EN   BIT(8)
 
#define GBL_EN   BIT(5)
 
#define TIMER_STS   BIT(0)
 
#define PM1_CNT_BLK   0x62
 
#define PM_TMR_BLK   0x64
 
#define PM_GPE0_BLK   0x68
 
#define PM_ACPI_SMI_CMD   0x6a
 
#define PM_ACPI_CONF   0x74
 
#define PM_ACPI_DECODE_STD   BIT(0)
 
#define PM_ACPI_GLOBAL_EN   BIT(1)
 
#define PM_ACPI_RTC_EN_EN   BIT(2)
 
#define PM_ACPI_SLPBTN_EN_EN   BIT(3)
 
#define PM_ACPI_TIMER_EN_EN   BIT(4)
 
#define PM_ACPI_MASK_ARB_DIS   BIT(6)
 
#define PM_ACPI_BIOS_RLS   BIT(7)
 
#define PM_ACPI_PWRBTNEN_EN   BIT(8)
 
#define PM_ACPI_REDUCED_HW_EN   BIT(9)
 
#define PM_ACPI_S5_LPC_PIN_MODE_SEL   BIT(10)
 
#define PM_ACPI_S5_LPC_PIN_MODE   BIT(11)
 
#define PM_ACPI_LPC_RST_DIS   BIT(12)
 
#define PM_ACPI_SEL_PWRGD_PAD   BIT(13)
 
#define PM_ACPI_SEL_SMU_THERMTRIP   BIT(14)
 
#define PM_ACPI_SW_S5PWRMUX_OVRD_N   BIT(15)
 
#define PM_ACPI_SW_S5PWRMUX   BIT(16)
 
#define PM_ACPI_EN_SHUTDOWN_MSG   BIT(17)
 
#define PM_ACPI_EN_SYNC_FLOOD   BIT(18)
 
#define PM_ACPI_FORCE_SPIUSEPIN_0   BIT(19)
 
#define PM_ACPI_EN_DF_INTRWAKE   BIT(20)
 
#define PM_ACPI_MASK_USB_S5_RST   BIT(21)
 
#define PM_ACPI_USE_RSMU_RESET   BIT(22)
 
#define PM_ACPI_RST_USB_S5   BIT(23)
 
#define PM_ACPI_BLOCK_PCIE_PME   BIT(24)
 
#define PM_ACPI_PCIE_WAK_MASK   BIT(25)
 
#define PM_ACPI_PCIE_WAK_INTR_DIS   BIT(26)
 
#define PM_ACPI_WAKE_AS_GEVENT   BIT(27)
 
#define PM_ACPI_NB_PME_GEVENT   BIT(28)
 
#define PM_ACPI_RTC_WAKE_EN   BIT(29)
 
#define PM_ACPI_USE_GATED_ALINK_CLK   BIT(30)
 
#define PM_ACPI_DELAY_GPP_OFF_TIME   BIT(31)
 
#define PM_SPI_PAD_PU_PD   0x90
 
#define PM_LPC_GATING   0xec
 
#define PM_LPC_AB_NO_BYPASS_EN   BIT(2)
 
#define PM_LPC_A20_EN   BIT(1)
 
#define PM_LPC_ENABLE   BIT(0)
 
#define PM1_LIMIT   16
 
#define GPE0_LIMIT   32
 
#define TOTAL_BITS(a)   (8 * sizeof(a))
 
#define FCH_LEGACY_UART_DECODE   (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */
 
#define GPP_CLK_CNTRL   0x00
 
#define GPP_CLK0_REQ_SHIFT   0
 
#define GPP_CLK1_REQ_SHIFT   2
 
#define GPP_CLK4_REQ_SHIFT   4
 
#define GPP_CLK2_REQ_SHIFT   6
 
#define GPP_CLK3_REQ_SHIFT   8
 
#define GPP_CLK5_REQ_SHIFT   10
 
#define GPP_CLK6_REQ_SHIFT   12
 
#define GPP_CLK_OUTPUT_COUNT   7
 
#define GPP_CLK_REQ_MASK(clk_shift)   (0x3 << (clk_shift))
 
#define GPP_CLK_REQ_ON(clk_shift)   (0x3 << (clk_shift))
 
#define GPP_CLK_REQ_EXT(clk_shift)   (0x1 << (clk_shift))
 
#define GPP_CLK_REQ_OFF(clk_shift)   (0x0 << (clk_shift))
 
#define MISC_CLKGATEDCNTL   0x2c
 
#define ALINKCLK_GATEOFFEN   BIT(16)
 
#define BLINKCLK_GATEOFFEN   BIT(17)
 
#define XTAL_PAD_S3_TURNOFF_EN   BIT(20)
 
#define XTAL_PAD_S5_TURNOFF_EN   BIT(21)
 
#define MISC_CGPLL_CONFIGURATION0   0x30
 
#define USB_PHY_CMCLK_S3_DIS   BIT(8)
 
#define USB_PHY_CMCLK_S0I3_DIS   BIT(9)
 
#define USB_PHY_CMCLK_S5_DIS   BIT(10)
 
#define MISC_CLK_CNTL0   0x40 /* named MISC_CLK_CNTL1 on Picasso */
 
#define BP_X48M0_S0I3_DIS   BIT(4)
 
#define BP_X48M0_OUTPUT_EN   BIT(2) /* 1=En, unlike Hudson, Kern */
 

Functions

void fch_pre_init (void)
 
void fch_early_init (void)
 
void fch_init (void *chip_info)
 
void fch_final (void *chip_info)
 
void enable_aoac_devices (void)
 
void wait_for_aoac_enabled (unsigned int dev)
 

Macro Definition Documentation

◆ ABCLKGATEEN

#define ABCLKGATEEN   BIT(16)

Definition at line 12 of file southbridge.h.

◆ ALINKCLK_GATEOFFEN

#define ALINKCLK_GATEOFFEN   BIT(16)

Definition at line 105 of file southbridge.h.

◆ BLINKCLK_GATEOFFEN

#define BLINKCLK_GATEOFFEN   BIT(17)

Definition at line 106 of file southbridge.h.

◆ BM_STS

#define BM_STS   BIT(4)

Definition at line 34 of file southbridge.h.

◆ BP_X48M0_OUTPUT_EN

#define BP_X48M0_OUTPUT_EN   BIT(2) /* 1=En, unlike Hudson, Kern */

Definition at line 115 of file southbridge.h.

◆ BP_X48M0_S0I3_DIS

#define BP_X48M0_S0I3_DIS   BIT(4)

Definition at line 114 of file southbridge.h.

◆ FCH_LEGACY_UART_DECODE

#define FCH_LEGACY_UART_DECODE   (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */

Definition at line 87 of file southbridge.h.

◆ FORCE_SLPSTATE_RETRY

#define FORCE_SLPSTATE_RETRY   BIT(25)

Definition at line 14 of file southbridge.h.

◆ GBL_EN

#define GBL_EN   BIT(5)

Definition at line 39 of file southbridge.h.

◆ GBL_STS

#define GBL_STS   BIT(5)

Definition at line 33 of file southbridge.h.

◆ GPE0_LIMIT

#define GPE0_LIMIT   32

Definition at line 84 of file southbridge.h.

◆ GPP_CLK0_REQ_SHIFT

#define GPP_CLK0_REQ_SHIFT   0

Definition at line 91 of file southbridge.h.

◆ GPP_CLK1_REQ_SHIFT

#define GPP_CLK1_REQ_SHIFT   2

Definition at line 92 of file southbridge.h.

◆ GPP_CLK2_REQ_SHIFT

#define GPP_CLK2_REQ_SHIFT   6

Definition at line 94 of file southbridge.h.

◆ GPP_CLK3_REQ_SHIFT

#define GPP_CLK3_REQ_SHIFT   8

Definition at line 95 of file southbridge.h.

◆ GPP_CLK4_REQ_SHIFT

#define GPP_CLK4_REQ_SHIFT   4

Definition at line 93 of file southbridge.h.

◆ GPP_CLK5_REQ_SHIFT

#define GPP_CLK5_REQ_SHIFT   10

Definition at line 96 of file southbridge.h.

◆ GPP_CLK6_REQ_SHIFT

#define GPP_CLK6_REQ_SHIFT   12

Definition at line 97 of file southbridge.h.

◆ GPP_CLK_CNTRL

#define GPP_CLK_CNTRL   0x00

Definition at line 90 of file southbridge.h.

◆ GPP_CLK_OUTPUT_COUNT

#define GPP_CLK_OUTPUT_COUNT   7

Definition at line 98 of file southbridge.h.

◆ GPP_CLK_REQ_EXT

#define GPP_CLK_REQ_EXT (   clk_shift)    (0x1 << (clk_shift))

Definition at line 101 of file southbridge.h.

◆ GPP_CLK_REQ_MASK

#define GPP_CLK_REQ_MASK (   clk_shift)    (0x3 << (clk_shift))

Definition at line 99 of file southbridge.h.

◆ GPP_CLK_REQ_OFF

#define GPP_CLK_REQ_OFF (   clk_shift)    (0x0 << (clk_shift))

Definition at line 102 of file southbridge.h.

◆ GPP_CLK_REQ_ON

#define GPP_CLK_REQ_ON (   clk_shift)    (0x3 << (clk_shift))

Definition at line 100 of file southbridge.h.

◆ MISC_CGPLL_CONFIGURATION0

#define MISC_CGPLL_CONFIGURATION0   0x30

Definition at line 109 of file southbridge.h.

◆ MISC_CLK_CNTL0

#define MISC_CLK_CNTL0   0x40 /* named MISC_CLK_CNTL1 on Picasso */

Definition at line 113 of file southbridge.h.

◆ MISC_CLKGATEDCNTL

#define MISC_CLKGATEDCNTL   0x2c

Definition at line 104 of file southbridge.h.

◆ PCIEXPWAK_DIS

#define PCIEXPWAK_DIS   BIT(14) /*AcpiPmEvtBlkx02 Pm1Enable */

Definition at line 36 of file southbridge.h.

◆ PCIEXPWAK_STS

#define PCIEXPWAK_STS   BIT(14)

Definition at line 30 of file southbridge.h.

◆ PM1_CNT_BLK

#define PM1_CNT_BLK   0x62

Definition at line 41 of file southbridge.h.

◆ PM1_LIMIT

#define PM1_LIMIT   16

Definition at line 83 of file southbridge.h.

◆ PM_ACPI_BIOS_RLS

#define PM_ACPI_BIOS_RLS   BIT(7)

Definition at line 52 of file southbridge.h.

◆ PM_ACPI_BLOCK_PCIE_PME

#define PM_ACPI_BLOCK_PCIE_PME   BIT(24)

Definition at line 69 of file southbridge.h.

◆ PM_ACPI_CONF

#define PM_ACPI_CONF   0x74

Definition at line 45 of file southbridge.h.

◆ PM_ACPI_DECODE_STD

#define PM_ACPI_DECODE_STD   BIT(0)

Definition at line 46 of file southbridge.h.

◆ PM_ACPI_DELAY_GPP_OFF_TIME

#define PM_ACPI_DELAY_GPP_OFF_TIME   BIT(31)

Definition at line 76 of file southbridge.h.

◆ PM_ACPI_EN_DF_INTRWAKE

#define PM_ACPI_EN_DF_INTRWAKE   BIT(20)

Definition at line 65 of file southbridge.h.

◆ PM_ACPI_EN_SHUTDOWN_MSG

#define PM_ACPI_EN_SHUTDOWN_MSG   BIT(17)

Definition at line 62 of file southbridge.h.

◆ PM_ACPI_EN_SYNC_FLOOD

#define PM_ACPI_EN_SYNC_FLOOD   BIT(18)

Definition at line 63 of file southbridge.h.

◆ PM_ACPI_FORCE_SPIUSEPIN_0

#define PM_ACPI_FORCE_SPIUSEPIN_0   BIT(19)

Definition at line 64 of file southbridge.h.

◆ PM_ACPI_GLOBAL_EN

#define PM_ACPI_GLOBAL_EN   BIT(1)

Definition at line 47 of file southbridge.h.

◆ PM_ACPI_LPC_RST_DIS

#define PM_ACPI_LPC_RST_DIS   BIT(12)

Definition at line 57 of file southbridge.h.

◆ PM_ACPI_MASK_ARB_DIS

#define PM_ACPI_MASK_ARB_DIS   BIT(6)

Definition at line 51 of file southbridge.h.

◆ PM_ACPI_MASK_USB_S5_RST

#define PM_ACPI_MASK_USB_S5_RST   BIT(21)

Definition at line 66 of file southbridge.h.

◆ PM_ACPI_NB_PME_GEVENT

#define PM_ACPI_NB_PME_GEVENT   BIT(28)

Definition at line 73 of file southbridge.h.

◆ PM_ACPI_PCIE_WAK_INTR_DIS

#define PM_ACPI_PCIE_WAK_INTR_DIS   BIT(26)

Definition at line 71 of file southbridge.h.

◆ PM_ACPI_PCIE_WAK_MASK

#define PM_ACPI_PCIE_WAK_MASK   BIT(25)

Definition at line 70 of file southbridge.h.

◆ PM_ACPI_PWRBTNEN_EN

#define PM_ACPI_PWRBTNEN_EN   BIT(8)

Definition at line 53 of file southbridge.h.

◆ PM_ACPI_REDUCED_HW_EN

#define PM_ACPI_REDUCED_HW_EN   BIT(9)

Definition at line 54 of file southbridge.h.

◆ PM_ACPI_RST_USB_S5

#define PM_ACPI_RST_USB_S5   BIT(23)

Definition at line 68 of file southbridge.h.

◆ PM_ACPI_RTC_EN_EN

#define PM_ACPI_RTC_EN_EN   BIT(2)

Definition at line 48 of file southbridge.h.

◆ PM_ACPI_RTC_WAKE_EN

#define PM_ACPI_RTC_WAKE_EN   BIT(29)

Definition at line 74 of file southbridge.h.

◆ PM_ACPI_S5_LPC_PIN_MODE

#define PM_ACPI_S5_LPC_PIN_MODE   BIT(11)

Definition at line 56 of file southbridge.h.

◆ PM_ACPI_S5_LPC_PIN_MODE_SEL

#define PM_ACPI_S5_LPC_PIN_MODE_SEL   BIT(10)

Definition at line 55 of file southbridge.h.

◆ PM_ACPI_SEL_PWRGD_PAD

#define PM_ACPI_SEL_PWRGD_PAD   BIT(13)

Definition at line 58 of file southbridge.h.

◆ PM_ACPI_SEL_SMU_THERMTRIP

#define PM_ACPI_SEL_SMU_THERMTRIP   BIT(14)

Definition at line 59 of file southbridge.h.

◆ PM_ACPI_SLPBTN_EN_EN

#define PM_ACPI_SLPBTN_EN_EN   BIT(3)

Definition at line 49 of file southbridge.h.

◆ PM_ACPI_SMI_CMD

#define PM_ACPI_SMI_CMD   0x6a

Definition at line 44 of file southbridge.h.

◆ PM_ACPI_SW_S5PWRMUX

#define PM_ACPI_SW_S5PWRMUX   BIT(16)

Definition at line 61 of file southbridge.h.

◆ PM_ACPI_SW_S5PWRMUX_OVRD_N

#define PM_ACPI_SW_S5PWRMUX_OVRD_N   BIT(15)

Definition at line 60 of file southbridge.h.

◆ PM_ACPI_TIMER_EN_EN

#define PM_ACPI_TIMER_EN_EN   BIT(4)

Definition at line 50 of file southbridge.h.

◆ PM_ACPI_USE_GATED_ALINK_CLK

#define PM_ACPI_USE_GATED_ALINK_CLK   BIT(30)

Definition at line 75 of file southbridge.h.

◆ PM_ACPI_USE_RSMU_RESET

#define PM_ACPI_USE_RSMU_RESET   BIT(22)

Definition at line 67 of file southbridge.h.

◆ PM_ACPI_WAKE_AS_GEVENT

#define PM_ACPI_WAKE_AS_GEVENT   BIT(27)

Definition at line 72 of file southbridge.h.

◆ PM_EVT_BLK

#define PM_EVT_BLK   0x60

Definition at line 28 of file southbridge.h.

◆ PM_GPE0_BLK

#define PM_GPE0_BLK   0x68

Definition at line 43 of file southbridge.h.

◆ PM_ISACONTROL

#define PM_ISACONTROL   0x04

Definition at line 11 of file southbridge.h.

◆ PM_LPC_A20_EN

#define PM_LPC_A20_EN   BIT(1)

Definition at line 80 of file southbridge.h.

◆ PM_LPC_AB_NO_BYPASS_EN

#define PM_LPC_AB_NO_BYPASS_EN   BIT(2)

Definition at line 79 of file southbridge.h.

◆ PM_LPC_ENABLE

#define PM_LPC_ENABLE   BIT(0)

Definition at line 81 of file southbridge.h.

◆ PM_LPC_GATING

#define PM_LPC_GATING   0xec

Definition at line 78 of file southbridge.h.

◆ PM_PCI_CTRL

#define PM_PCI_CTRL   0x08

Definition at line 13 of file southbridge.h.

◆ PM_SERIRQ_CONF

#define PM_SERIRQ_CONF   0x54

Definition at line 17 of file southbridge.h.

◆ PM_SERIRQ_ENABLE

#define PM_SERIRQ_ENABLE   BIT(7)

Definition at line 27 of file southbridge.h.

◆ PM_SERIRQ_MODE

#define PM_SERIRQ_MODE   BIT(6)

Definition at line 26 of file southbridge.h.

◆ PM_SERIRQ_NUM_BITS_17

#define PM_SERIRQ_NUM_BITS_17   0x0000

Definition at line 18 of file southbridge.h.

◆ PM_SERIRQ_NUM_BITS_18

#define PM_SERIRQ_NUM_BITS_18   0x0004

Definition at line 19 of file southbridge.h.

◆ PM_SERIRQ_NUM_BITS_19

#define PM_SERIRQ_NUM_BITS_19   0x0008

Definition at line 20 of file southbridge.h.

◆ PM_SERIRQ_NUM_BITS_20

#define PM_SERIRQ_NUM_BITS_20   0x000c

Definition at line 21 of file southbridge.h.

◆ PM_SERIRQ_NUM_BITS_21

#define PM_SERIRQ_NUM_BITS_21   0x0010

Definition at line 22 of file southbridge.h.

◆ PM_SERIRQ_NUM_BITS_22

#define PM_SERIRQ_NUM_BITS_22   0x0014

Definition at line 23 of file southbridge.h.

◆ PM_SERIRQ_NUM_BITS_23

#define PM_SERIRQ_NUM_BITS_23   0x0018

Definition at line 24 of file southbridge.h.

◆ PM_SERIRQ_NUM_BITS_24

#define PM_SERIRQ_NUM_BITS_24   0x001c

Definition at line 25 of file southbridge.h.

◆ PM_SPI_PAD_PU_PD

#define PM_SPI_PAD_PU_PD   0x90

Definition at line 77 of file southbridge.h.

◆ PM_TMR_BLK

#define PM_TMR_BLK   0x64

Definition at line 42 of file southbridge.h.

◆ PWR_RESET_CFG

#define PWR_RESET_CFG   0x10

Definition at line 15 of file southbridge.h.

◆ PWRBTN_EN

#define PWRBTN_EN   BIT(8)

Definition at line 38 of file southbridge.h.

◆ PWRBTN_STS

#define PWRBTN_STS   BIT(8)

Definition at line 32 of file southbridge.h.

◆ RTC_EN

#define RTC_EN   BIT(10)

Definition at line 37 of file southbridge.h.

◆ RTC_STS

#define RTC_STS   BIT(10)

Definition at line 31 of file southbridge.h.

◆ TIMER_STS [1/2]

#define TIMER_STS   BIT(0)

Definition at line 40 of file southbridge.h.

◆ TIMER_STS [2/2]

#define TIMER_STS   BIT(0)

Definition at line 40 of file southbridge.h.

◆ TOGGLE_ALL_PWR_GOOD

#define TOGGLE_ALL_PWR_GOOD   (1 << 1)

Definition at line 16 of file southbridge.h.

◆ TOTAL_BITS

#define TOTAL_BITS (   a)    (8 * sizeof(a))

Definition at line 85 of file southbridge.h.

◆ USB_PHY_CMCLK_S0I3_DIS

#define USB_PHY_CMCLK_S0I3_DIS   BIT(9)

Definition at line 111 of file southbridge.h.

◆ USB_PHY_CMCLK_S3_DIS

#define USB_PHY_CMCLK_S3_DIS   BIT(8)

Definition at line 110 of file southbridge.h.

◆ USB_PHY_CMCLK_S5_DIS

#define USB_PHY_CMCLK_S5_DIS   BIT(10)

Definition at line 112 of file southbridge.h.

◆ WAK_STS

#define WAK_STS   BIT(15) /*AcpiPmEvtBlkx00 Pm1Status */

Definition at line 29 of file southbridge.h.

◆ XTAL_PAD_S3_TURNOFF_EN

#define XTAL_PAD_S3_TURNOFF_EN   BIT(20)

Definition at line 107 of file southbridge.h.

◆ XTAL_PAD_S5_TURNOFF_EN

#define XTAL_PAD_S5_TURNOFF_EN   BIT(21)

Definition at line 108 of file southbridge.h.

Function Documentation

◆ enable_aoac_devices()

void enable_aoac_devices ( void  )

Definition at line 41 of file aoac.c.

◆ fch_early_init()

void fch_early_init ( void  )

Definition at line 71 of file early_fch.c.

References CONFIG, fch_print_pmxc0_status(), i2c_soc_early_init(), lpc_disable_spi_rom_sharing(), pm_set_power_failure_state(), and show_spi_speeds_and_modes().

Referenced by bootblock_soc_init().

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◆ fch_final()

void fch_final ( void *  chip_info)

Definition at line 304 of file fch.c.

◆ fch_init()

void fch_init ( void *  chip_info)

Definition at line 290 of file fch.c.

◆ fch_pre_init()

void fch_pre_init ( void  )

Definition at line 35 of file early_fch.c.

References clear_uart_legacy_config(), CONFIG, configure_espi_with_mb_hook(), enable_acpimmio_decode_pm04(), enable_aoac_devices(), fch_disable_kb_rst(), fch_disable_legacy_dma_io(), fch_enable_cf9_io(), fch_enable_legacy_io(), fch_smbus_init(), fch_spi_early_init(), lpc_configure_decodes(), lpc_early_init(), reset_i2c_peripherals(), and set_uart_config().

Referenced by bootblock_soc_early_init().

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◆ wait_for_aoac_enabled()

void wait_for_aoac_enabled ( unsigned int  dev)

Definition at line 35 of file aoac.c.

References is_aoac_device_enabled(), and udelay().

Referenced by enable_aoac_devices(), and uart_enable().

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