fixme.c

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/* SPDX-License-Identifier: GPL-2.0-only */
 
#include <arch/hpet.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
#include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <AGESA.h>
#include <amdlib.h>
 
void amd_initcpuio(void)
{
        UINT64 MsrReg;
        UINT32 PciData;
        PCI_ADDR PciAddress;
        AMD_CONFIG_PARAMS StdHeader;
 
        /* Enable legacy video routing: D18F1xF4 VGA Enable */
        PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4);
        PciData = 1;
        LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
        /* The platform BIOS needs to ensure the memory ranges of SB800 legacy
         * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
         * set to non-posted regions.
         */
        PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
        PciData = 0x00FEDF00;   // last address before processor local APIC at FEE00000
        PciData |= 1 << 7;      // set NP (non-posted) bit
        LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
        PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
        PciData = (HPET_BASE_ADDRESS >> 8) | 3; // lowest NP address is HPET at FED00000
        LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
        /* Map the remaining PCI hole as posted MMIO */
        PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
        PciData = 0x00FECF00;   // last address before non-posted range
        LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
        LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
        MsrReg = (MsrReg >> 8) | 3;
        PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
        PciData = (UINT32) MsrReg;
        LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
        /* Send all IO (0000-FFFF) to southbridge. */
        PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
        PciData = 0x0000F000;
        LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
        PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
        PciData = 0x00000003;
        LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
}
 
void amd_initenv(void)
{
        AMD_INTERFACE_PARAMS AmdParamStruct;
        PCI_ADDR PciAddress;
        UINT32 PciValue;
 
        /* Initialize Subordinate Bus Number and Secondary Bus Number
         * In platform BIOS this address is allocated by PCI enumeration code
         Modify D1F0x18
         */
        PciAddress.Address.Bus = 0;
        PciAddress.Address.Device = 1;
        PciAddress.Address.Function = 0;
        PciAddress.Address.Register = 0x18;
        /* Write to D1F0x18 */
        LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
        PciValue |= 0x00010100;
        LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 
        /* Initialize GMM Base Address for Legacy Bridge Mode
         *      Modify B1D5F0x18
         */
        PciAddress.Address.Bus = 1;
        PciAddress.Address.Device = 5;
        PciAddress.Address.Function = 0;
        PciAddress.Address.Register = 0x18;
 
        LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
        PciValue |= 0x96000000;
        LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 
        /* Initialize FB Base Address for Legacy Bridge Mode
         * Modify B1D5F0x10
         */
        PciAddress.Address.Register = 0x10;
        LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
        PciValue |= 0x80000000;
        LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 
        /* Initialize GMM Base Address for PCIe Mode
         *      Modify B0D1F0x18
         */
        PciAddress.Address.Bus = 0;
        PciAddress.Address.Device = 1;
        PciAddress.Address.Function = 0;
        PciAddress.Address.Register = 0x18;
 
        LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
        PciValue |= 0x96000000;
        LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 
        /* Initialize FB Base Address for PCIe Mode
         *      Modify B0D1F0x10
         */
        PciAddress.Address.Register = 0x10;
        LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
        PciValue |= 0x80000000;
        LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 
        /* Initialize MMIO Base and Limit Address
         *      Modify B0D1F0x20
         */
        PciAddress.Address.Bus = 0;
        PciAddress.Address.Device = 1;
        PciAddress.Address.Function = 0;
        PciAddress.Address.Register = 0x20;
 
        LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
        PciValue |= 0x96009600;
        LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
 
        /* Initialize MMIO Prefetchable Memory Limit and Base
         *      Modify B0D1F0x24
         */
        PciAddress.Address.Register = 0x24;
        LibAmdPciRead(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
        PciValue |= 0x8FF18001;
        LibAmdPciWrite(AccessWidth32, PciAddress, &PciValue, &AmdParamStruct.StdHeader);
}