coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
bootblock.c
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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #include <bootblock_common.h>
6 
7 #define GPIO_DEV PNP_DEV(0x2e, IT8786E_GPIO)
8 #define SERIAL1_DEV PNP_DEV(0x2e, IT8786E_SP1)
9 #define SERIAL3_DEV PNP_DEV(0x2e, IT8786E_SP3)
10 #define SERIAL4_DEV PNP_DEV(0x2e, IT8786E_SP4)
11 #define SERIAL5_DEV PNP_DEV(0x2e, IT8786E_SP5)
12 #define SERIAL6_DEV PNP_DEV(0x2e, IT8786E_SP6)
13 
15 {
19  ite_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE);
20 
21  /*
22  * FIXME:
23  * IT8786E has 6 COM ports, COM1/3/5 have default IO base 0x3f8 and
24  * COM2/4/6 have 0x2f8. When enabling devices before setting resources
25  * from devicetree, the output on debugging COM1 becomes very slow due
26  * to the same IO bases for multiple COM ports. For now set different
27  * hardcoded IO bases for COM3/4/5/6 ports, they will be set later to
28  * desired values from devicetree. They can be also turned off.
29  */
34 }
void ite_enable_serial(pnp_devfn_t dev, u16 iobase)
Definition: early_serial.c:61
void ite_kill_watchdog(pnp_devfn_t dev)
Definition: early_serial.c:129
void ite_conf_clkin(pnp_devfn_t dev, u8 predivide)
Definition: early_serial.c:55
void ite_enable_3vsbsw(pnp_devfn_t dev)
Definition: early_serial.c:85
#define ITE_UART_CLK_PREDIVIDE_24
Definition: ite.h:10
__weak void bootblock_mainboard_early_init(void)
Definition: bootblock.c:16
#define SERIAL6_DEV
Definition: bootblock.c:12
#define GPIO_DEV
Definition: bootblock.c:7
#define SERIAL3_DEV
Definition: bootblock.c:9
#define SERIAL4_DEV
Definition: bootblock.c:10
#define SERIAL5_DEV
Definition: bootblock.c:11
#define SERIAL1_DEV
Definition: bootblock.c:8