coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
bootblock.c
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/cache.h>
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#include <
bootblock_common.h
>
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#include <soc/clk.h>
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#include <
soc/wakeup.h
>
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#include <soc/cpu.h>
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/* convenient shorthand (in MB) */
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#define SRAM_START (EXYNOS5_SRAM_BASE >> 20)
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#define SRAM_SIZE 1
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#define SRAM_END (SRAM_START + SRAM_SIZE)
/* plus one... */
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void
bootblock_soc_init
(
void
)
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{
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if
(
get_wakeup_state
() ==
WAKEUP_DIRECT
) {
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wakeup
();
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/* Never returns. */
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}
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/* set up dcache and MMU */
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mmu_init
();
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mmu_disable_range
(0,
SRAM_START
);
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mmu_config_range
(
SRAM_START
,
SRAM_SIZE
,
DCACHE_WRITEBACK
);
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mmu_config_range
(
SRAM_END
, 4096 -
SRAM_END
,
DCACHE_OFF
);
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dcache_mmu_enable
();
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/* For most ARM systems, we have to initialize firmware media source
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* (ex, SPI, SD/MMC, or eMMC) now; but for Exynos platform, that is
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* already handled by iROM so there's no need to setup again.
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*/
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}
dcache_mmu_enable
void dcache_mmu_enable(void)
Definition:
cache.c:53
mmu_config_range
void mmu_config_range(u32 start_mb, u32 size_mb, enum dcache_policy policy)
Definition:
mmu.c:221
mmu_init
void mmu_init(void)
Definition:
mmu.c:242
mmu_disable_range
void mmu_disable_range(u32 start_mb, u32 size_mb)
Definition:
mmu.c:211
DCACHE_WRITEBACK
@ DCACHE_WRITEBACK
Definition:
cache.h:364
DCACHE_OFF
@ DCACHE_OFF
Definition:
cache.h:363
bootblock_common.h
bootblock_soc_init
void bootblock_soc_init(void)
Definition:
bootblock.c:27
SRAM_SIZE
#define SRAM_SIZE
Definition:
bootblock.c:11
SRAM_START
#define SRAM_START
Definition:
bootblock.c:10
SRAM_END
#define SRAM_END
Definition:
bootblock.c:12
wakeup.h
get_wakeup_state
int get_wakeup_state(void)
Definition:
wakeup.c:17
WAKEUP_DIRECT
@ WAKEUP_DIRECT
Definition:
wakeup.h:15
wakeup
void wakeup(void)
Definition:
wakeup.c:6
src
soc
samsung
exynos5420
bootblock.c
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