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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Go to the source code of this file.
Macros | |
#define | SCTLR_M (1 << 0) /* MMU enable */ |
#define | SCTLR_A (1 << 1) /* Alignment check enable */ |
#define | SCTLR_C (1 << 2) /* Data/unified cache enable */ |
#define | SCTLR_CP15BEN (1 << 5) /* CP15 barrier enable */ |
#define | SCTLR_B (1 << 7) /* Endianness */ |
#define | SCTLR_SW (1 << 10) /* SWP and SWPB enable */ |
#define | SCTLR_Z (1 << 11) /* Branch prediction enable */ |
#define | SCTLR_I (1 << 12) /* Instruction cache enable */ |
#define | SCTLR_V (1 << 13) /* Low/high exception vectors */ |
#define | SCTLR_RR (1 << 14) /* Round Robin select */ |
#define | SCTLR_HA (1 << 17) /* Hardware Access flag enable */ |
#define | SCTLR_WXN (1 << 19) /* Write permission implies XN */ |
#define | SCTLR_UWXN |
#define | SCTLR_FI (1 << 21) /* Fast interrupt config enable */ |
#define | SCTLR_U (1 << 22) /* Unaligned access behavior */ |
#define | SCTLR_VE (1 << 24) /* Interrupt vectors enable */ |
#define | SCTLR_EE (1 << 25) /* Exception endianness */ |
#define | SCTLR_NMFI (1 << 27) /* Non-maskable FIQ support */ |
#define | SCTLR_TRE (1 << 28) /* TEX remap enable */ |
#define | SCTLR_AFE (1 << 29) /* Access flag enable */ |
#define | SCTLR_TE (1 << 30) /* Thumb exception enable */ |
Enumerations | |
enum | dcache_policy { DCACHE_OFF , DCACHE_WRITEBACK , DCACHE_WRITETHROUGH } |
#define SCTLR_FI (1 << 21) /* Fast interrupt config enable */ |
#define SCTLR_UWXN |
#define SCTLR_WXN (1 << 19) /* Write permission implies XN */ |
enum dcache_policy |
Definition at line 57 of file cache.c.
References dcache_clean_all(), dcache_clean_invalidate_all(), dsb, iciallu(), isb, read_sctlr(), SCTLR_C, and SCTLR_I.
Referenced by arch_prog_run(), arch_segment_loaded(), and load_ipq_blob().
Definition at line 49 of file cache.c.
References dcache_clean_invalidate_all(), read_sctlr(), SCTLR_C, SCTLR_M, and write_sctlr().
Referenced by arch_prog_run(), mainboard_init(), setup_mmu(), usb_cbfs_open(), and wakeup().
Definition at line 53 of file cache.c.
References read_sctlr(), SCTLR_C, SCTLR_M, and write_sctlr().
Referenced by bootblock_soc_init(), enable_cache(), mainboard_enable(), romstage(), setup_mmu(), and usb_cbfs_open().
Definition at line 141 of file cache.h.
Referenced by dcache_op_mva().
Definition at line 153 of file cache.h.
Referenced by dcache_op_mva(), mmu_create_subtable(), and mmu_fill_table().
Definition at line 165 of file cache.h.
Referenced by dcache_op_mva().
Definition at line 54 of file cache.h.
Referenced by icache_invalidate_all(), and tlb_invalidate_all().
Definition at line 177 of file cache.h.
Referenced by cache_sync_instructions(), icache_invalidate_all(), and low_power_start().
Definition at line 60 of file cache.h.
Referenced by icache_invalidate_all(), tlb_invalidate_all(), write_csselr(), write_l2actlr(), write_l2ctlr(), and write_sctlr().
void mmu_config_range | ( | u32 | start_mb, |
u32 | size_mb, | ||
enum dcache_policy | policy | ||
) |
Definition at line 221 of file mmu.c.
References assert, ATTR_BLOCK, attrs, BIOS_DEBUG, BLOCK_SHIFT, BLOCK_SIZE, DIV_ROUND_UP, GiB, MiB, mmu_fill_table(), name, printk, ttb_buff, and value.
Referenced by bootblock_mainboard_init(), bootblock_soc_init(), decompressor_soc_init(), display_startup(), enable_cache(), exynos_displayport_init(), main(), mainboard_enable(), mtk_mmu_after_dram(), mtk_mmu_disable_l2c_sram(), mtk_mmu_init(), mtk_soc_after_dram(), platform_romstage_main(), qc_mmu_dram_config_post_dram_init(), qcs405_mmu_init(), rk_display_init(), romstage(), sc7180_mmu_init(), sc7280_mmu_init(), setup_dram_mappings(), setup_mmu(), shrm_fw_load_reset(), soc_mmu_init(), and tegra210_mmu_config().
void mmu_config_range_kb | ( | u32 | start_kb, |
u32 | size_kb, | ||
enum dcache_policy | policy | ||
) |
Definition at line 174 of file mmu.c.
References ALIGN_UP, assert, ATTR_PAGE, attrs, BIOS_DEBUG, BLOCK_SIZE, CONFIG, KiB, mask, mmu_fill_table(), mmu_validate_create_sub_table(), name, PAGE_SHIFT, PAGE_SIZE, and printk.
Referenced by bootblock_soc_init(), and setup_mmu().
Definition at line 211 of file mmu.c.
References assert, BIOS_DEBUG, BLOCK_SHIFT, BLOCK_SIZE, DIV_ROUND_UP, GiB, MiB, mmu_fill_table(), printk, and ttb_buff.
Referenced by bootblock_soc_init(), enable_cache(), romstage(), setup_dram_mappings(), and setup_mmu().
Definition at line 198 of file mmu.c.
References BIOS_DEBUG, BLOCK_SIZE, DIV_ROUND_UP, KiB, mask, mmu_fill_table(), mmu_validate_create_sub_table(), PAGE_SHIFT, PAGE_SIZE, and printk.
Referenced by setup_mmu().
Definition at line 303 of file cache.h.
References val.
Referenced by exception_data_abort().
Definition at line 311 of file cache.h.
References val.
Referenced by exception_prefetch_abort().
Definition at line 195 of file cache.h.
References val.
Referenced by dcache_line_bytes().
Definition at line 271 of file cache.h.
References val.
Referenced by exception_data_abort().
Definition at line 279 of file cache.h.
References val.
Referenced by exception_data_abort().
Definition at line 287 of file cache.h.
References val.
Referenced by exception_prefetch_abort().
Definition at line 295 of file cache.h.
References val.
Referenced by exception_prefetch_abort().
Definition at line 241 of file cache.h.
References val.
Referenced by configure_l2actlr().
Definition at line 222 of file cache.h.
References val.
Referenced by configure_l2ctlr().
Definition at line 88 of file cache.h.
Referenced by mmu_init().
Definition at line 256 of file cache.h.
References val.
Referenced by cache_sync_instructions(), dcache_mmu_disable(), dcache_mmu_enable(), exception_init(), and low_power_start().
Definition at line 70 of file cache.h.
Referenced by low_power_start(), and tlb_invalidate_all().
Definition at line 76 of file cache.h.
Referenced by mmu_create_subtable(), and mmu_fill_table().
Definition at line 82 of file cache.h.
References val.
Referenced by mmu_init().
Definition at line 249 of file cache.h.
Referenced by configure_l2actlr().
Definition at line 230 of file cache.h.
Referenced by configure_l2ctlr(), and exynos5250_config_l2_cache().
Definition at line 102 of file cache.h.
References val.
Referenced by mmu_init().
Definition at line 264 of file cache.h.
Referenced by dcache_mmu_disable(), dcache_mmu_enable(), exception_init(), and low_power_start().
Definition at line 125 of file cache.h.
References val.
Referenced by mmu_init().