coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
romstage.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <acpi/acpi.h>
4 #include <amdblocks/memmap.h>
5 #include <amdblocks/pmlib.h>
6 #include <arch/cpu.h>
7 #include <commonlib/helpers.h>
8 #include <console/console.h>
9 #include <fsp/api.h>
10 #include <program_loading.h>
11 #include <timestamp.h>
12 #include <types.h>
13 
15 {
17 
18  post_code(0x40);
19 
20  console_init();
21 
22  post_code(0x42);
23 
24  /* Snapshot chipset state prior to any FSP call. */
26 
27  post_code(0x43);
29 
31 
32  post_code(0x44);
33  run_ramstage();
34 
35  post_code(0x50); /* Should never see this post code. */
36 }
static int acpi_is_wakeup_s3(void)
Definition: acpi.h:9
#define asmlinkage
Definition: cpu.h:8
asmlinkage void car_stage_entry(void)
Definition: romstage.c:61
void fsp_memory_init(bool s3wake)
Definition: memory_init.c:350
void console_init(void)
Definition: init.c:49
void timestamp_add_now(enum timestamp_id id)
Definition: timestamp.c:141
void fill_chipset_state(void)
Definition: chipset_state.c:12
#define post_code(value)
Definition: post_code.h:12
void run_ramstage(void)
Definition: prog_loaders.c:85
void memmap_stash_early_dram_usage(void)
Definition: memmap.c:15
@ TS_ROMSTAGE_START