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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <clock_common.h>
Data Fields | |
u32 | cmd_dfsr |
u8 | _res0 [0x20 - 0x1c] |
u32 | perf_dfsr [8] |
u8 | _res1 [0x60 - 0x40] |
u32 | perf_m_dfsr [8] |
u8 | _res2 [0xa0 - 0x80] |
u32 | perf_n_dfsr [8] |
u8 | _res3 [0xe0 - 0xc0] |
u32 | perf_d_dfsr [8] |
u8 | _res4 [0x130 - 0x100] |
Definition at line 23 of file clock_common.h.
u8 clock_rcg_dfsr::_res0[0x20 - 0x1c] |
Definition at line 25 of file clock_common.h.
u8 clock_rcg_dfsr::_res1[0x60 - 0x40] |
Definition at line 27 of file clock_common.h.
u8 clock_rcg_dfsr::_res2[0xa0 - 0x80] |
Definition at line 29 of file clock_common.h.
u8 clock_rcg_dfsr::_res3[0xe0 - 0xc0] |
Definition at line 31 of file clock_common.h.
u8 clock_rcg_dfsr::_res4[0x130 - 0x100] |
Definition at line 33 of file clock_common.h.
u32 clock_rcg_dfsr::cmd_dfsr |
Definition at line 24 of file clock_common.h.
Referenced by agera_pll_enable().
u32 clock_rcg_dfsr::perf_d_dfsr[8] |
Definition at line 32 of file clock_common.h.
Referenced by agera_pll_enable().
u32 clock_rcg_dfsr::perf_dfsr[8] |
Definition at line 26 of file clock_common.h.
Referenced by agera_pll_enable().
u32 clock_rcg_dfsr::perf_m_dfsr[8] |
Definition at line 28 of file clock_common.h.
Referenced by agera_pll_enable().
u32 clock_rcg_dfsr::perf_n_dfsr[8] |
Definition at line 30 of file clock_common.h.
Referenced by agera_pll_enable().