coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
model_2065x.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef _CPU_INTEL_MODEL_2065X_H
4 #define _CPU_INTEL_MODEL_2065X_H
5 
6 /* Arrandale bus clock is fixed at 133MHz */
7 #define IRONLAKE_BCLK 133
8 
9 #define MSR_CORE_THREAD_COUNT 0x35
10 #define MSR_FEATURE_CONFIG 0x13c
11 #define MSR_FLEX_RATIO 0x194
12 #define FLEX_RATIO_LOCK (1 << 20)
13 #define FLEX_RATIO_EN (1 << 16)
14 #define MSR_TEMPERATURE_TARGET 0x1a2
15 #define IA32_FERR_CAPABILITY 0x1f1
16 #define FERR_ENABLE (1 << 0)
17 
18 #define MSR_PLATFORM_INFO 0xce
19 #define PLATFORM_INFO_SET_TDP (1 << 29)
20 
21 #define MSR_MISC_PWR_MGMT 0x1aa
22 #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)
23 #define MSR_TURBO_POWER_CURRENT_LIMIT 0x1ac
24 #define MSR_TURBO_RATIO_LIMIT 0x1ad
25 #define MSR_POWER_CTL 0x1fc
26 
27 #define MSR_PKGC3_IRTL 0x60a
28 #define MSR_PKGC6_IRTL 0x60b
29 #define MSR_PKGC7_IRTL 0x60c
30 #define IRTL_VALID (1 << 15)
31 #define IRTL_1_NS (0 << 10)
32 #define IRTL_32_NS (1 << 10)
33 #define IRTL_1024_NS (2 << 10)
34 #define IRTL_32768_NS (3 << 10)
35 #define IRTL_1048576_NS (4 << 10)
36 #define IRTL_33554432_NS (5 << 10)
37 #define IRTL_RESPONSE_MASK (0x3ff)
38 
39 /* long duration in low dword, short duration in high dword */
40 #define MSR_PKG_POWER_LIMIT 0x610
41 #define PKG_POWER_LIMIT_MASK 0x7fff
42 #define PKG_POWER_LIMIT_EN (1 << 15)
43 #define PKG_POWER_LIMIT_CLAMP (1 << 16)
44 #define PKG_POWER_LIMIT_TIME_SHIFT 17
45 #define PKG_POWER_LIMIT_TIME_MASK 0x7f
46 
47 /* P-state configuration */
48 #define PSS_MAX_ENTRIES 16
49 #define PSS_RATIO_STEP 1
50 #define PSS_LATENCY_TRANSITION 10
51 #define PSS_LATENCY_BUSMASTER 10
52 
53 /* Lock MSRs */
55 
56 /* Configure power limits for turbo mode */
57 void set_power_limits(u8 power_limit_1_time);
58 
59 /* Sanity check config options. */
60 #if (CONFIG_SMM_TSEG_SIZE <= CONFIG_SMM_RESERVED_SIZE)
61 # error "CONFIG_SMM_TSEG_SIZE <= CONFIG_SMM_RESERVED_SIZE"
62 #endif
63 #if (CONFIG_SMM_TSEG_SIZE < 0x800000)
64 # error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB"
65 #endif
66 #if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0)
67 # error "CONFIG_SMM_TSEG_SIZE is not a power of 2"
68 #endif
69 
70 #endif
void set_power_limits(u8 power_limit_1_time)
Definition: haswell_init.c:313
void intel_model_2065x_finalize_smm(void)
Definition: finalize.c:14
uint8_t u8
Definition: stdint.h:45