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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <baseboard/variants.h>
#include <cpu/x86/smm.h>
#include <ec/google/chromeec/smm.h>
#include <intelblocks/smihandler.h>
#include <soc/pm.h>
#include <soc/gpio.h>
#include <variant/ec.h>
#include <variant/gpio.h>
Go to the source code of this file.
Functions | |
void | mainboard_smi_gpi_handler (const struct gpi_status *sts) |
void | mainboard_smi_sleep (u8 slp_typ) |
int | mainboard_smi_apmc (u8 apmc) |
void | mainboard_smi_espi_handler (void) |
int mainboard_smi_apmc | ( | u8 | apmc | ) |
Definition at line 32 of file smihandler.c.
References chromeec_smi_apmc(), CONFIG, MAINBOARD_EC_SCI_EVENTS, and MAINBOARD_EC_SMI_EVENTS.
Definition at line 40 of file smihandler.c.
References chromeec_smi_process_events(), and CONFIG.
void mainboard_smi_gpi_handler | ( | const struct gpi_status * | sts | ) |
Definition at line 12 of file smihandler.c.
References chromeec_smi_process_events(), CONFIG, EC_SMI_GPI, and gpi_status_get().
Definition at line 19 of file smihandler.c.
References chromeec_smi_sleep(), CONFIG, gpio_configure_pads(), MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS, and variant_sleep_gpio_table().