coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Functions | |
static int | hudson_sata_enable (void) |
static int | hudson_ide_enable (void) |
void | hudson_lpc_port80 (void) |
void | hudson_lpc_decode (void) |
void | hudson_pci_port80 (void) |
void | hudson_clk_output_48Mhz (void) |
void | hudson_read_mode (u32 mode) |
void | hudson_set_spi100 (u16 norm, u16 fast, u16 alt, u16 tpm) |
void | hudson_disable_4dw_burst (void) |
void | hudson_set_readspeed (u16 norm, u16 fast) |
void | lpc_wideio_512_window (uint16_t base) |
void | lpc_wideio_16_window (uint16_t base) |
void | hudson_tpm_decode_spi (void) |
void | hudson_enable (struct device *dev) |
void | s3_resume_init_data (void *FchParams) |
#define ACPI_CPU_CONTROL (HUDSON_ACPI_IO_BASE + 0x08) /* 6 bytes */ |
#define ACPI_GPE0_BLK (HUDSON_ACPI_IO_BASE + 0x10) /* 8 bytes */ |
#define ACPI_PM1_CNT_BLK (HUDSON_ACPI_IO_BASE + 0x04) /* 2 bytes */ |
#define ACPI_PM_EVT_BLK (HUDSON_ACPI_IO_BASE + 0x00) /* 4 bytes */ |
#define ACPI_PM_TMR_BLK (HUDSON_ACPI_IO_BASE + 0x18) /* 4 bytes */ |
Definition at line 179 of file early_setup.c.
Definition at line 222 of file early_setup.c.
References base, hudson_spibase(), read16(), SPI100_HOST_PREF_CONFIG, SPI_RD4DW_EN_HOST, and write16().
Definition at line 39 of file hudson.c.
References __fallthrough, BIOS_DEBUG, BIT, pci_path::devfn, device::enabled, hudson_disable_usb(), device::path, device_path::pci, PCI_DEVFN, PCI_DEVICE_ID, PCI_DID_AMD_HUDSON_SD, PCI_DID_AMD_SB900_USB_20_5, PCI_DID_AMD_YANGTZE_SD, pci_read_config16(), PM_HUD_SD_FLASH_CTRL, PM_MANUAL_RESET, pm_read8(), pm_write8(), PM_YANG_SD_FLASH_CTRL, printk, USB_EN_DEVFN_12_0, USB_EN_DEVFN_12_2, USB_EN_DEVFN_13_0, USB_EN_DEVFN_13_2, USB_EN_DEVFN_16_0, and USB_EN_DEVFN_16_2.
Definition at line 68 of file early_setup.c.
References DECODE_ENABLE_SERIAL_PORT0, DECODE_ENABLE_SERIAL_PORT1, DECODE_ENABLE_SERIAL_PORT5, DECODE_ENABLE_SERIAL_PORT7, LPC_IO_PORT_DECODE_ENABLE, PCI_DEV, pci_write_config32(), pm_read8(), and pm_write8().
Referenced by bootblock_early_southbridge_init().
Definition at line 57 of file early_setup.c.
References PCI_DEV, pci_read_config8(), and pci_write_config8().
Referenced by bootblock_early_southbridge_init(), and bootblock_mainboard_early_init().
Definition at line 12 of file early_setup.c.
References PCI_DEV, pci_read_config8(), and pci_write_config8().
Referenced by bootblock_early_southbridge_init().
Definition at line 241 of file early_setup.c.
References base, hudson_spibase(), read32(), SPI_CNTRL0, SPI_READ_MODE_MASK, and write32().
Definition at line 231 of file early_setup.c.
References base, hudson_spibase(), read16(), SPI_CNTRL1, SPI_CNTRL1_SPEED_MASK, SPI_FAST_SPEED_SH, SPI_NORM_SPEED_SH, and write16().
Definition at line 210 of file early_setup.c.
References base, hudson_spibase(), read16(), SPI100_ENABLE, SPI100_SPEED_CONFIG, SPI_ALT_SPEED_NEW_SH, SPI_FAST_SPEED_NEW_SH, SPI_NORM_SPEED_NEW_SH, SPI_TPM_SPEED_NEW_SH, SPI_USE_SPI100, and write16().
Definition at line 249 of file early_setup.c.
References PCI_DEV, pci_read_config32(), pci_write_config32(), ROUTE_TPM_2_SPI, and SPIROM_BASE_ADDRESS_REGISTER.
Definition at line 173 of file early_setup.c.
References assert, base, IS_ALIGNED, and lpc_wideio_window().
Definition at line 167 of file early_setup.c.
References assert, base, IS_ALIGNED, and lpc_wideio_window().