coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
ramstage.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <device/device.h>
4 #include <soc/ramstage.h>
5 #include <carrier/gpio.h>
6 
7 static void init_mainboard(void *chip_info)
8 {
10 }
11 
13 {
14  /*
15  * CPU Power Management Configuration correspond to the BIOS Setup menu settings
16  * in the AMI UEFI v112.
17  * TODO: move these FSP options to device tree
18  */
19  silconfig->EnableCx = 1; /* Enable CPU power states */
20  silconfig->C1e = 1; /* enable Enhanced C-states */
21  /*
22  * Attention! Do not change PkgCStateLimit! This causes spikes in the power
23  * consumption of the SoC when the system comes out of power saving mode, and
24  * voltage sagging at the output of DC-DC converters on the COMe module. In the
25  * AMI BIOS Setup shows this parameter, but does not allow changing it.
26  */
27  silconfig->PkgCStateLimit = 0; /* Max Pkg Cstate : PkgC0C1 */
28  silconfig->MaxCoreCState = 3; /* Max Core C-State : C6 */
29  silconfig->CStateAutoDemotion = 0; /* Disable C1 and C3 Auto-demotion */
30  silconfig->CStateUnDemotion = 0; /* Disable C1 and C3 Un-demotion */
31  silconfig->PkgCStateDemotion = 1; /* enable package Cstate demotion */
32  silconfig->PkgCStateUnDemotion = 1; /* enable package Cstate undemotion */
33  silconfig->PmSupport = 1; /* GT PM Support */
34  silconfig->EnableRenderStandby = 1; /* enable render standby */
35  silconfig->LPSS_S0ixEnable = 1; /* LPSS IOSF PMCTL S0ix Enable */
36  silconfig->InitS3Cpu = 1; /* initialize CPU during S3 resume */
37 
38  /* Override High Precision Timer options */
39  silconfig->HpetBdfValid = 1;
40  silconfig->HpetBusNumber = 0xFA;
41  silconfig->HpetDeviceNumber = 0x0F;
42  silconfig->HpetFunctionNumber = 0;
43 
44  /* Override APIC options */
45  silconfig->IoApicId = 1;
46  silconfig->IoApicBdfValid = 1;
47  silconfig->IoApicBusNumber = 0xFA;
48  silconfig->IoApicDeviceNumber = 0x1F;
49  silconfig->IoApicFunctionNumber = 0;
50 }
51 
54 };
__weak void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
Definition: ramstage.c:162
#define FSP_S_CONFIG
Definition: fsp_upd.h:9
struct chip_operations mainboard_ops
Definition: ramstage.c:11
void carrier_gpio_configure(void)
Definition: gpio.c:264
static void init_mainboard(void *chip_info)
Definition: ramstage.c:7
void(* init)(void *chip_info)
Definition: device.h:25