coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
romstage.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <
arch/romstage.h
>
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#include <
intelblocks/rtc.h
>
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#include <soc/romstage.h>
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#include <soc/soc_util.h>
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#include "
chip.h
"
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void
platform_fsp_memory_init_params_cb
(FSPM_UPD *mupd,
uint32_t
version
)
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{
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const
config_t
*
config
=
config_of_soc
();
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FSP_M_CONFIG
*m_cfg = &mupd->FspmConfig;
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mupd->FspmUpdVersion = FSP_UPD_VERSION;
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// ErrorLevel - 0 (disable) to 8 (verbose)
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m_cfg->PcdFspMrcDebugPrintErrorLevel = 0;
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m_cfg->PcdFspKtiDebugPrintErrorLevel = 0;
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mainboard_memory_init_params
(mupd);
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m_cfg->VTdConfig.VTdSupport =
config
->vtd_support;
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m_cfg->VTdConfig.CoherencySupport =
config
->coherency_support;
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m_cfg->VTdConfig.ATS =
config
->ats_support;
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}
romstage.h
FSP_M_CONFIG
#define FSP_M_CONFIG
Definition:
fsp_upd.h:8
config_of_soc
#define config_of_soc()
Definition:
device.h:394
version
unsigned int version[2]
Definition:
edid.c:55
mainboard_memory_init_params
void mainboard_memory_init_params(FSPM_UPD *mupd)
Definition:
romstage.c:22
config
enum board_config config
Definition:
memory.c:448
platform_fsp_memory_init_params_cb
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
Definition:
romstage.c:279
rtc.h
uint32_t
unsigned int uint32_t
Definition:
stdint.h:14
ec_kontron_it8516e_config
Definition:
chip.h:8
chip.h
src
soc
intel
xeon_sp
skx
romstage.c
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