coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
romstage.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <soc/romstage.h>
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#include <
string.h
>
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#include <
spd_bin.h
>
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#include <fsp/soc_binding.h>
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void
mainboard_memory_init_params
(FSPM_UPD *mupd)
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{
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FSP_M_CONFIG
*mem_cfg = &mupd->FspmConfig;
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const
FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd;
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/* Rcomp resistor */
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const
u16
rcomp_resistor
[] = { 121, 81, 100 };
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/* Rcomp target */
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const
u16
rcomp_target
[] = { 100, 40, 20, 20, 26 };
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/* SPD was saved in S0/S5 path, skips it when resumes from S3 */
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if
(arch_upd->BootMode ==
FSP_BOOT_ON_S3_RESUME
)
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return
;
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memcpy
(&mem_cfg->RcompResistor,
rcomp_resistor
,
sizeof
(
rcomp_resistor
));
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memcpy
(&mem_cfg->RcompTarget,
rcomp_target
,
sizeof
(
rcomp_target
));
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/* Read spd block to get memory config */
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struct
spd_block
blk = {
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.
addr_map
= { 0x50, 0x52, },
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};
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mem_cfg->DqPinsInterleaved = 1;
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mem_cfg->CaVrefConfig = 2;
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get_spd_smbus
(&blk);
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mem_cfg->MemorySpdDataLen = blk.
len
;
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mem_cfg->MemorySpdPtr00 = (
uintptr_t
)blk.
spd_array
[0];
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mem_cfg->MemorySpdPtr10 = (
uintptr_t
)blk.
spd_array
[1];
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dump_spd_info
(&blk);
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}
memcpy
void * memcpy(void *dest, const void *src, size_t n)
Definition:
memcpy.c:7
FSP_BOOT_ON_S3_RESUME
@ FSP_BOOT_ON_S3_RESUME
Definition:
api.h:23
FSP_M_CONFIG
#define FSP_M_CONFIG
Definition:
fsp_upd.h:8
mainboard_memory_init_params
void mainboard_memory_init_params(FSPM_UPD *mupd)
Definition:
romstage.c:22
rcomp_target
static const u16 rcomp_target[]
Definition:
memory.c:26
rcomp_resistor
static const u16 rcomp_resistor[]
Definition:
memory.c:23
spd_bin.h
get_spd_smbus
void get_spd_smbus(struct spd_block *blk)
Definition:
smbuslib.c:72
dump_spd_info
void dump_spd_info(struct spd_block *blk)
Definition:
spd_bin.c:10
uintptr_t
unsigned long uintptr_t
Definition:
stdint.h:21
u16
uint16_t u16
Definition:
stdint.h:48
string.h
spd_block
Definition:
ddr4.c:86
spd_block::addr_map
u8 addr_map[CONFIG_DIMM_MAX]
Definition:
spd_bin.h:39
spd_block::spd_array
u8 * spd_array[CONFIG_DIMM_MAX]
Definition:
spd_bin.h:40
spd_block::len
uint16_t len
Definition:
ddr4.c:89
src
mainboard
google
fizz
romstage.c
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