coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
api.h
Go to the documentation of this file.
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 
3 #ifndef _FSP2_0_API_H_
4 #define _FSP2_0_API_H_
5 
6 #include <stddef.h>
7 #include <stdint.h>
8 #include <fsp/soc_binding.h>
9 #include <soc/intel/common/mma.h>
10 
11 #define FSP_SUCCESS EFI_SUCCESS
12 #define FSP_INVALID_PARAMETER EFI_INVALID_PARAMETER
13 #define FSP_DEVICE_ERROR EFI_DEVICE_ERROR
14 #define FSP_NOT_FOUND EFI_NOT_FOUND
15 #define FSP_NOT_STARTED EFI_NOT_STARTED
16 #define FSP_UNSUPPORTED EFI_UNSUPPORTED
17 
26 };
27 
30  READY_TO_BOOT = 0x40,
31  END_OF_FIRMWARE = 0xF0
32 };
33 
34 /* Main FSP stages */
35 void preload_fspm(void);
36 void fsp_memory_init(bool s3wake);
37 void preload_fsps(void);
38 void fsp_silicon_init(void);
39 
40 /*
41  * Load FSP-S from stage cache or CBFS. This allows SoCs to load FSPS-S
42  * separately from calling silicon init. It might be required in cases where
43  * stage cache is no longer available by the point SoC calls into silicon init.
44  */
45 void fsps_load(void);
46 
47 /* Callbacks for updating stage-specific parameters */
49 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd);
50 /* Callbacks for SoC/Mainboard specific overrides */
52 /* Check if MultiPhase Si Init is enabled */
54 /*
55  * The following functions are used when FSP_PLATFORM_MEMORY_SETTINGS_VERSION
56  * is employed allowing the mainboard and SoC to supply their own version
57  * for memory settings respectively. The valid values are 0-15 for each
58  * function.
59  */
62 
63 /* Callback after processing FSP notify */
65 
66 /* Initialize memory margin analysis settings. */
67 void setup_mma(FSP_M_CONFIG *memory_cfg);
68 /* Update the SOC specific logo param and load the logo. */
69 void soc_load_logo(FSPS_UPD *supd);
70 /* Update the SOC specific memory config param for mma. */
72  struct mma_config_param *mma_cfg);
73 
74 /*
75  * As per FSP integration guide:
76  * If bootloader needs to take control of APs back, a full AP re-initialization is
77  * required after FSP-S is completed and control has been transferred back to bootloader
78  */
79 void do_mpinit_after_fsp(void);
80 
81 /*
82  * # DOCUMENTATION:
83  *
84  * This file defines the interface between coreboot and the FSP 2.0 wrapper
85  * fsp_memory_init(), fsp_silicon_init(), and fsp_notify() are the main entry
86  * points and map 1:1 to the FSP entry points of the same name.
87  *
88  * ### fsp_memory_init():
89  * - s3wake: boolean indicating if the system is waking from resume
90  *
91  * This function is responsible for loading and executing the memory
92  * initialization code from the FSP-M binary. It expects this binary to reside
93  * in cbfs as FSP_M_FILE.
94  *
95  * The function takes one parameter, which is described above, but does not
96  * take in memory parameters as an argument. The memory parameters can be filled
97  * in with platform_fsp_memory_init_params_cb(). This is a callback symbol
98  * that fsp_memory_init() will call. The platform must provide this symbol.
99  *
100  *
101  * ### fsp_silicon_init():
102  *
103  * This function is responsible for loading and executing the silicon
104  * initialization code from the FSP-S binary. It expects this binary to reside
105  * in cbfs as FSP_S_FILE.
106  *
107  * Like fsp_memory_init(), it provides a callback to fill in FSP-specific
108  * parameters, via platform_fsp_silicon_init_params_cb(). The platform must
109  * also provide this symbol.
110  *
111  *
112  * ### fsp_notify():
113  * - phase: Which FSP notification phase
114  *
115  * This function is responsible for loading and executing the notify code from
116  * the FSP-S binary. It expects that fsp_silicon_init() has already been called
117  * successfully, and that the FSP-S binary is still loaded into memory.
118  */
119 
120 #endif /* _FSP2_0_API_H_ */
void do_mpinit_after_fsp(void)
Definition: fsp_mpinit.c:11
void fsp_silicon_init(void)
Definition: silicon_init.c:242
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
Definition: fsp_s_params.c:14
bool fsp_is_multi_phase_init_enabled(void)
Definition: silicon_init.c:75
fsp_boot_mode
Definition: api.h:18
@ FSP_BOOT_WITH_MINIMAL_CONFIGURATION
Definition: api.h:20
@ FSP_BOOT_ON_S3_RESUME
Definition: api.h:23
@ FSP_BOOT_ON_S4_RESUME
Definition: api.h:22
@ FSP_BOOT_IN_RECOVERY_MODE
Definition: api.h:25
@ FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES
Definition: api.h:21
@ FSP_BOOT_WITH_FULL_CONFIGURATION
Definition: api.h:19
@ FSP_BOOT_ON_FLASH_UPDATE
Definition: api.h:24
void fsps_load(void)
Definition: silicon_init.c:204
void setup_mma(FSP_M_CONFIG *memory_cfg)
Definition: mma_core.c:22
fsp_notify_phase
Definition: api.h:28
@ END_OF_FIRMWARE
Definition: api.h:31
@ AFTER_PCI_ENUM
Definition: api.h:29
@ READY_TO_BOOT
Definition: api.h:30
uint8_t fsp_memory_mainboard_version(void)
Definition: memory_init.c:186
uint8_t fsp_memory_soc_version(void)
Definition: memory_init.c:192
void preload_fsps(void)
Definition: silicon_init.c:233
void platform_fsp_multi_phase_init_cb(uint32_t phase_index)
Definition: silicon_init.c:27
void soc_load_logo(FSPS_UPD *supd)
Definition: silicon_init.c:252
void preload_fspm(void)
Definition: memory_init.c:341
void fsp_memory_init(bool s3wake)
Definition: memory_init.c:350
void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, struct mma_config_param *mma_cfg)
Definition: fsp_params.c:165
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
Definition: fsp_m_params.c:66
void platform_fsp_notify_status(enum fsp_notify_phase phase)
Definition: notify.c:112
#define FSP_M_CONFIG
Definition: fsp_upd.h:8
unsigned int version[2]
Definition: edid.c:55
unsigned int uint32_t
Definition: stdint.h:14
unsigned char uint8_t
Definition: stdint.h:8