3 #ifndef AMD_BLOCK_PCI_UTIL_H
4 #define AMD_BLOCK_PCI_UTIL_H
7 #include <soc/amd_pci_int_defs.h>
11 #define PCI_INTR_INDEX 0xc00
12 #define PCI_INTR_DATA 0xc01
const struct irq_idx_name * sb_get_apic_reg_association(size_t *size)
void acpigen_write_pci_GNB_PRT(const struct device *dev)
void write_pci_int_idx(u8 index, int mode, u8 data)
void write_pci_cfg_irqs(void)
void write_pci_int_table(void)
void populate_pirq_data(void)
unsigned int pci_calculate_irq(const struct pci_routing_info *routing_info, unsigned int pin)
u8 read_pci_int_idx(u8 index, int mode)
const struct pci_routing_info * get_pci_routing_info(unsigned int devfn)
const struct pirq_struct * pirq_data_ptr
void acpigen_write_pci_FCH_PRT(const struct device *dev)
struct pci_routing_info __packed
const struct pci_routing_info * get_pci_routing_table(size_t *entries)
Each PCI bridge has its INTx lines routed to one of the GNB IO-APIC PCI groups.