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| #define | SMRBASE 0x14 /* System Memory RCOMP Base Address Register, 32 bit? */ |
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| #define | MCHCFGNS 0x52 /* MCH (scrubber) configuration register, 16 bit */ |
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| #define | PAM_0 0x59 |
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| #define | DRB_ROW_0 0x60 /* DRAM Row Boundary register, 8 bit */ |
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| #define | DRB_ROW_1 0x61 |
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| #define | DRB_ROW_2 0x62 |
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| #define | DRB_ROW_3 0x63 |
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| #define | DRB_ROW_4 0x64 |
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| #define | DRB_ROW_5 0x65 |
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| #define | DRB_ROW_6 0x66 |
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| #define | DRB_ROW_7 0x67 |
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| #define | DRA 0x70 /* DRAM Row Attributes registers, 4 x 8 bit */ |
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| #define | DRT 0x78 /* DRAM Timing register, 32 bit */ |
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| #define | DRC 0x7C /* DRAM Controller Mode register, 32 bit */ |
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| #define | DRDCTL 0x80 /* DRAM Read Timing Control register, 16 bit? (if similar to 855PM) */ |
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| #define | CKDIS 0x8C /* Clock disable register, 8 bit */ |
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| #define | SMRAMC 0x9D |
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| #define | ESMRAMC 0x9E |
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| #define | APSIZE 0xB4 |
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| #define | TOLM 0xC4 /* Top of Low Memory register, 16 bit */ |
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| #define | REMAPBASE 0xC6 /* Remap Base Address register, 16 bit */ |
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| #define | REMAPLIMIT 0xC8 /* Remap Limit Address register, 16 bit */ |
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| #define | SKPD 0xDE /* Scratchpad register, 16 bit */ |
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| #define | DVNP 0xE0 /* Device Not Present, 16 bit */ |
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| #define | MCHTST 0xF4 /* MCH Test Register, 32 bit? (if similar to 855PM) */ |
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| #define | DRT_CAS_2_5 (0<<4) |
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| #define | DRT_CAS_2_0 (1<<4) |
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| #define | DRT_CAS_MASK (3<<4) |
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| #define | RAM_COMMAND_NOP (1<<4) |
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| #define | RAM_COMMAND_PRECHARGE (2<<4) |
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| #define | RAM_COMMAND_MRS (3<<4) |
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| #define | RAM_COMMAND_EMRS (4<<4) |
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| #define | RAM_COMMAND_CBR (6<<4) |
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| #define | RAM_COMMAND_NORMAL (7<<4) |
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| #define | DRC_DONE (1 << 29) |
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| #define | SMRCTL 0x20 /* System Memory RCOMP Control Register? */ |
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| #define | DQCMDSTR 0x30 /* Strength control for DQ and CMD signal groups? */ |
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| #define | CKESTR 0x31 /* Strength control for CKE signal group? */ |
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| #define | CSBSTR 0x32 /* Strength control for CS# signal group? */ |
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| #define | CKSTR 0x33 /* Strength control for CK signal group? */ |
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| #define | RCVENSTR 0x34 /* Strength control for RCVEnOut# signal group? */ |
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| #define | FERR_GLOBAL 0x40 /* First global error register, 32 bits */ |
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| #define | NERR_GLOBAL 0x44 /* Next global error register, 32 bits */ |
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| #define | DRAM_FERR 0x80 /* DRAM first error register, 8 bits */ |
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| #define | DRAM_NERR 0x82 /* DRAM next error register, 8 bits */ |
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| #define | APSIZE1 0x74 |
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1.9.1