displayport.h File Reference

#include <soc/sor.h>

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Data Structures
struct	tegra_dc_dp_data

Macros
#define	DPAUX_INTR_EN_AUX   (0x1)
#define	DPAUX_INTR_AUX   (0x5)
#define	DPAUX_DP_AUXDATA_WRITE_W(i)   (0x9 + 4*(i))
#define	DPAUX_DP_AUXDATA_READ_W(i)   (0x19 + 4*(i))
#define	DPAUX_DP_AUXADDR   (0x29)
#define	DPAUX_DP_AUXCTL   (0x2d)
#define	DPAUX_DP_AUXCTL_CMDLEN_SHIFT   (0)
#define	DPAUX_DP_AUXCTL_CMDLEN_FIELD   (0xff)
#define	DPAUX_DP_AUXCTL_CMD_SHIFT   (12)
#define	DPAUX_DP_AUXCTL_CMD_MASK   (0xf << 12)
#define	DPAUX_DP_AUXCTL_CMD_I2CWR   (0 << 12)
#define	DPAUX_DP_AUXCTL_CMD_I2CRD   (1 << 12)
#define	DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT   (2 << 12)
#define	DPAUX_DP_AUXCTL_CMD_MOTWR   (4 << 12)
#define	DPAUX_DP_AUXCTL_CMD_MOTRD   (5 << 12)
#define	DPAUX_DP_AUXCTL_CMD_MOTREQWSTAT   (6 << 12)
#define	DPAUX_DP_AUXCTL_CMD_AUXWR   (8 << 12)
#define	DPAUX_DP_AUXCTL_CMD_AUXRD   (9 << 12)
#define	DPAUX_DP_AUXCTL_TRANSACTREQ_SHIFT   (16)
#define	DPAUX_DP_AUXCTL_TRANSACTREQ_MASK   (0x1 << 16)
#define	DPAUX_DP_AUXCTL_TRANSACTREQ_DONE   (0 << 16)
#define	DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING   (1 << 16)
#define	DPAUX_DP_AUXCTL_RST_SHIFT   (31)
#define	DPAUX_DP_AUXCTL_RST_DEASSERT   (0 << 31)
#define	DPAUX_DP_AUXCTL_RST_ASSERT   (1 << 31)
#define	DPAUX_DP_AUXSTAT   (0x31)
#define	DPAUX_DP_AUXSTAT_HPD_STATUS_SHIFT   (28)
#define	DPAUX_DP_AUXSTAT_HPD_STATUS_UNPLUG   (0 << 28)
#define	DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED   (1 << 28)
#define	DPAUX_DP_AUXSTAT_AUXCTL_STATE_SHIFT   (20)
#define	DPAUX_DP_AUXSTAT_AUXCTL_STATE_MASK   (0xf << 20)
#define	DPAUX_DP_AUXSTAT_AUXCTL_STATE_IDLE   (0 << 20)
#define	DPAUX_DP_AUXSTAT_AUXCTL_STATE_SYNC   (1 << 20)
#define	DPAUX_DP_AUXSTAT_AUXCTL_STATE_START1   (2 << 20)
#define	DPAUX_DP_AUXSTAT_AUXCTL_STATE_COMMAND   (3 << 20)
#define	DPAUX_DP_AUXSTAT_AUXCTL_STATE_ADDRESS   (4 << 20)
#define	DPAUX_DP_AUXSTAT_AUXCTL_STATE_LENGTH   (5 << 20)
#define	DPAUX_DP_AUXSTAT_AUXCTL_STATE_WRITE1   (6 << 20)
#define	DPAUX_DP_AUXSTAT_AUXCTL_STATE_READ1   (7 << 20)
#define	DPAUX_DP_AUXSTAT_AUXCTL_STATE_GET_M   (8 << 20)
#define	DPAUX_DP_AUXSTAT_AUXCTL_STATE_STOP1   (9 << 20)
#define	DPAUX_DP_AUXSTAT_AUXCTL_STATE_STOP2   (10 << 20)
#define	DPAUX_DP_AUXSTAT_AUXCTL_STATE_REPLY   (11 << 20)
#define	DPAUX_DP_AUXSTAT_AUXCTL_STATE_CLEANUP   (12 << 20)
#define	DPAUX_DP_AUXSTAT_REPLYTYPE_SHIFT   (16)
#define	DPAUX_DP_AUXSTAT_REPLYTYPE_MASK   (0xf << 16)
#define	DPAUX_DP_AUXSTAT_REPLYTYPE_ACK   (0 << 16)
#define	DPAUX_DP_AUXSTAT_REPLYTYPE_NACK   (1 << 16)
#define	DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER   (2 << 16)
#define	DPAUX_DP_AUXSTAT_REPLYTYPE_I2CNACK   (4 << 16)
#define	DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER   (8 << 16)
#define	DPAUX_DP_AUXSTAT_NO_STOP_ERROR_SHIFT   (11)
#define	DPAUX_DP_AUXSTAT_NO_STOP_ERROR_NOT_PENDING   (0 << 11)
#define	DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING   (1 << 11)
#define	DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_SHIFT   (10)
#define	DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_NOT_PENDING   (0 << 10)
#define	DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING   (1 << 10)
#define	DPAUX_DP_AUXSTAT_RX_ERROR_SHIFT   (9)
#define	DPAUX_DP_AUXSTAT_RX_ERROR_NOT_PENDING   (0 << 9)
#define	DPAUX_DP_AUXSTAT_RX_ERROR_PENDING   (1 << 9)
#define	DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_SHIFT   (8)
#define	DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_NOT_PENDING   (0 << 8)
#define	DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING   (1 << 8)
#define	DPAUX_DP_AUXSTAT_REPLY_M_SHIFT   (0)
#define	DPAUX_DP_AUXSTAT_REPLY_M_MASK   (0xff << 0)
#define	DPAUX_HPD_CONFIG   (0x3d)
#define	DPAUX_HPD_IRQ_CONFIG   (0x41)
#define	DPAUX_DP_AUX_CONFIG   (0x45)
#define	DPAUX_HYBRID_PADCTL   (0x49)
#define	DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_SHIFT   (15)
#define	DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_DISABLE   (0 << 15)
#define	DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_ENABLE   (1 << 15)
#define	DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_SHIFT   (14)
#define	DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_DISABLE   (0 << 14)
#define	DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_ENABLE   (1 << 14)
#define	DPAUX_HYBRID_PADCTL_AUX_CMH_SHIFT   (12)
#define	DPAUX_HYBRID_PADCTL_AUX_CMH_DEFAULT_MASK   (0x3 << 12)
#define	DPAUX_HYBRID_PADCTL_AUX_CMH_V0_60   (0 << 12)
#define	DPAUX_HYBRID_PADCTL_AUX_CMH_V0_64   (1 << 12)
#define	DPAUX_HYBRID_PADCTL_AUX_CMH_V0_70   (2 << 12)
#define	DPAUX_HYBRID_PADCTL_AUX_CMH_V0_56   (3 << 12)
#define	DPAUX_HYBRID_PADCTL_AUX_DRVZ_SHIFT   (8)
#define	DPAUX_HYBRID_PADCTL_AUX_DRVZ_DEFAULT_MASK   (0x7 << 8)
#define	DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_78   (0 << 8)
#define	DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_60   (1 << 8)
#define	DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_54   (2 << 8)
#define	DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_45   (3 << 8)
#define	DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_50   (4 << 8)
#define	DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_42   (5 << 8)
#define	DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_39   (6 << 8)
#define	DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_34   (7 << 8)
#define	DPAUX_HYBRID_PADCTL_AUX_DRVI_SHIFT   (2)
#define	DPAUX_HYBRID_PADCTL_AUX_DRVI_DEFAULT_MASK   (0x3f << 2)
#define	DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_SHIFT   (1)
#define	DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_DISABLE   (0 << 1)
#define	DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_ENABLE   (1 << 1)
#define	DPAUX_HYBRID_PADCTL_MODE_SHIFT   (0)
#define	DPAUX_HYBRID_PADCTL_MODE_AUX   (0)
#define	DPAUX_HYBRID_PADCTL_MODE_I2C   (1)
#define	DPAUX_HYBRID_SPARE   (0x4d)
#define	DPAUX_HYBRID_SPARE_PAD_PWR_POWERUP   (0)
#define	DPAUX_HYBRID_SPARE_PAD_PWR_POWERDOWN   (1)
#define	DPAUX_HPD_CONFIG_UNPLUG_MIN_TIME_SHIFT   (16)
#define	DP_AUX_DEFER_MAX_TRIES   7
#define	DP_AUX_TIMEOUT_MAX_TRIES   2
#define	DP_POWER_ON_MAX_TRIES   3
#define	DP_CLOCK_RECOVERY_MAX_TRIES   7
#define	DP_CLOCK_RECOVERY_TOT_TRIES   15
#define	DP_AUX_MAX_BYTES   16
#define	DP_AUX_TIMEOUT_MS   40
#define	DP_DPCP_RETRY_SLEEP_NS   400
#define	EDP_PWR_ON_TO_AUX_TIME_MS   (200+10)
#define	EDP_PWR_ON_TO_ML_TIME_MS   (200+10)
#define	EDP_PWR_OFF_TO_ON_TIME_MS   (500+10)
#define	NV_DPCD_REV   (0x00000000)
#define	NV_DPCD_REV_MAJOR_SHIFT   (4)
#define	NV_DPCD_REV_MAJOR_MASK   (0xf << 4)
#define	NV_DPCD_REV_MINOR_SHIFT   (0)
#define	NV_DPCD_REV_MINOR_MASK   (0xf)
#define	NV_DPCD_MAX_LINK_BANDWIDTH   (0x00000001)
#define	NV_DPCD_MAX_LINK_BANDWIDTH_VAL_1_62_GPBS   (0x00000006)
#define	NV_DPCD_MAX_LINK_BANDWIDTH_VAL_2_70_GPBS   (0x0000000a)
#define	NV_DPCD_MAX_LINK_BANDWIDTH_VAL_5_40_GPBS   (0x00000014)
#define	NV_DPCD_MAX_LANE_COUNT   (0x00000002)
#define	NV_DPCD_MAX_LANE_COUNT_MASK   (0x1f)
#define	NV_DPCD_MAX_LANE_COUNT_LANE_1   (0x00000001)
#define	NV_DPCD_MAX_LANE_COUNT_LANE_2   (0x00000002)
#define	NV_DPCD_MAX_LANE_COUNT_LANE_4   (0x00000004)
#define	NV_DPCD_MAX_LANE_COUNT_TPS3_SUPPORTED_YES   (0x00000001 << 6)
#define	NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_NO   (0x00000000 << 7)
#define	NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES   (0x00000001 << 7)
#define	NV_DPCD_MAX_DOWNSPREAD   (0x00000003)
#define	NV_DPCD_MAX_DOWNSPREAD_VAL_NONE   (0x00000000)
#define	NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT   (0x00000001)
#define	NV_DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_F   (0x00000000 << 6)
#define	NV_DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_T   (0x00000001 << 6)
#define	NV_DPCD_EDP_CONFIG_CAP   (0x0000000D)
#define	NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_NO   (0x00000000)
#define	NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES   (0x00000001)
#define	NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_NO   (0x00000000 << 1)
#define	NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES   (0x00000001 << 1)
#define	NV_DPCD_TRAINING_AUX_RD_INTERVAL   (0x0000000E)
#define	NV_DPCD_LINK_BANDWIDTH_SET   (0x00000100)
#define	NV_DPCD_LANE_COUNT_SET   (0x00000101)
#define	NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_F   (0x00000000 << 7)
#define	NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_T   (0x00000001 << 7)
#define	NV_DPCD_TRAINING_PATTERN_SET   (0x00000102)
#define	NV_DPCD_TRAINING_PATTERN_SET_TPS_MASK   0x3
#define	NV_DPCD_TRAINING_PATTERN_SET_TPS_NONE   (0x00000000)
#define	NV_DPCD_TRAINING_PATTERN_SET_TPS_TP1   (0x00000001)
#define	NV_DPCD_TRAINING_PATTERN_SET_TPS_TP2   (0x00000002)
#define	NV_DPCD_TRAINING_PATTERN_SET_TPS_TP3   (0x00000003)
#define	NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_F   (0x00000000 << 5)
#define	NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_T   (0x00000001 << 5)
#define	NV_DPCD_TRAINING_LANE0_SET   (0x00000103)
#define	NV_DPCD_TRAINING_LANE1_SET   (0x00000104)
#define	NV_DPCD_TRAINING_LANE2_SET   (0x00000105)
#define	NV_DPCD_TRAINING_LANE3_SET   (0x00000106)
#define	NV_DPCD_TRAINING_LANEX_SET_DC_SHIFT   0
#define	NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_T   (0x00000001 << 2)
#define	NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_F   (0x00000000 << 2)
#define	NV_DPCD_TRAINING_LANEX_SET_PE_SHIFT   3
#define	NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_T   (0x00000001 << 5)
#define	NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_F   (0x00000000 << 5)
#define	NV_DPCD_DOWNSPREAD_CTRL   (0x00000107)
#define	NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_NONE   (0x00000000 << 4)
#define	NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_LT_0_5   (0x00000001 << 4)
#define	NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET   (0x00000108)
#define	NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET_ANSI_8B10B   1
#define	NV_DPCD_EDP_CONFIG_SET   (0x0000010A)
#define	NV_DPCD_EDP_CONFIG_SET_ASC_RESET_DISABLE   (0x00000000)
#define	NV_DPCD_EDP_CONFIG_SET_ASC_RESET_ENABLE   (0x00000001)
#define	NV_DPCD_EDP_CONFIG_SET_FRAMING_CHANGE_DISABLE   (0x00000000 << 1)
#define	NV_DPCD_EDP_CONFIG_SET_FRAMING_CHANGE_ENABLE   (0x00000001 << 1)
#define	NV_DPCD_TRAINING_LANE0_1_SET2   (0x0000010F)
#define	NV_DPCD_TRAINING_LANE2_3_SET2   (0x00000110)
#define	NV_DPCD_LANEX_SET2_PC2_SHIFT   0
#define	NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_T   (0x00000001 << 2)
#define	NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_F   (0x00000000 << 2)
#define	NV_DPCD_LANEXPLUS1_SET2_PC2_SHIFT   4
#define	NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_T   (0x00000001 << 6)
#define	NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_F   (0x00000000 << 6)
#define	NV_DPCD_SINK_COUNT   (0x00000200)
#define	NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR   (0x00000201)
#define	NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_AUTO_TEST_NO   (0x00000000 << 1)
#define	NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_AUTO_TEST_YES   (0x00000001 << 1)
#define	NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_CP_NO   (0x00000000 << 2)
#define	NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_CP_YES   (0x00000001 << 2)
#define	NV_DPCD_LANE0_1_STATUS   (0x00000202)
#define	NV_DPCD_LANE2_3_STATUS   (0x00000203)
#define	NV_DPCD_STATUS_LANEX_CR_DONE_SHIFT   0
#define	NV_DPCD_STATUS_LANEX_CR_DONE_NO   (0x00000000)
#define	NV_DPCD_STATUS_LANEX_CR_DONE_YES   (0x00000001)
#define	NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT   1
#define	NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_NO   (0x00000000 << 1)
#define	NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_YES   (0x00000001 << 1)
#define	NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT   2
#define	NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_NO   (0x00000000 << 2)
#define	NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_YES   (0x00000001 << 2)
#define	NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_SHIFT   4
#define	NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_NO   (0x00000000 << 4)
#define	NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES   (0x00000001 << 4)
#define	NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_SHIFT   5
#define	NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_NO   (0x00000000 << 5)
#define	NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES   (0x00000001 << 5)
#define	NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_SHIFT   6
#define	NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_NO   (0x00000000 << 6)
#define	NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES   (0x00000001 << 6)
#define	NV_DPCD_LANE_ALIGN_STATUS_UPDATED   (0x00000204)
#define	NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_NO   (0x00000000)
#define	NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_YES   (0x00000001)
#define	NV_DPCD_SINK_STATUS   (0x00000205)
#define	NV_DPCD_SINK_STATUS_PORT0_IN_SYNC   (0x1 << 0)
#define	NV_DPCD_LANE0_1_ADJUST_REQ   (0x00000206)
#define	NV_DPCD_LANE2_3_ADJUST_REQ   (0x00000207)
#define	NV_DPCD_ADJUST_REQ_LANEX_DC_SHIFT   0
#define	NV_DPCD_ADJUST_REQ_LANEX_DC_MASK   0x3
#define	NV_DPCD_ADJUST_REQ_LANEX_PE_SHIFT   2
#define	NV_DPCD_ADJUST_REQ_LANEX_PE_MASK   (0x3 << 2)
#define	NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_SHIFT   4
#define	NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_MASK   (0x3 << 4)
#define	NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_SHIFT   6
#define	NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_MASK   (0x3 << 6)
#define	NV_DPCD_ADJUST_REQ_POST_CURSOR2   (0x0000020C)
#define	NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_MASK   0x3
#define	NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_SHIFT(i)   (i*2)
#define	NV_DPCD_TEST_REQUEST   (0x00000218)
#define	NV_DPCD_SOURCE_IEEE_OUI   (0x00000300)
#define	NV_DPCD_SINK_IEEE_OUI   (0x00000400)
#define	NV_DPCD_BRANCH_IEEE_OUI   (0x00000500)
#define	NV_DPCD_SET_POWER   (0x00000600)
#define	NV_DPCD_SET_POWER_VAL_RESERVED   (0x00000000)
#define	NV_DPCD_SET_POWER_VAL_D0_NORMAL   (0x00000001)
#define	NV_DPCD_SET_POWER_VAL_D3_PWRDWN   (0x00000002)
#define	NV_DPCD_HDCP_BKSV_OFFSET   (0x00068000)
#define	NV_DPCD_HDCP_RPRIME_OFFSET   (0x00068005)
#define	NV_DPCD_HDCP_AKSV_OFFSET   (0x00068007)
#define	NV_DPCD_HDCP_AN_OFFSET   (0x0006800C)
#define	NV_DPCD_HDCP_VPRIME_OFFSET   (0x00068014)
#define	NV_DPCD_HDCP_BCAPS_OFFSET   (0x00068028)
#define	NV_DPCD_HDCP_BSTATUS_OFFSET   (0x00068029)
#define	NV_DPCD_HDCP_BINFO_OFFSET   (0x0006802A)
#define	NV_DPCD_HDCP_KSV_FIFO_OFFSET   (0x0006802C)
#define	NV_DPCD_HDCP_AINFO_OFFSET   (0x0006803B)

Enumerations
enum	{ driveCurrent_Level0 = 0 , driveCurrent_Level1 = 1 , driveCurrent_Level2 = 2 , driveCurrent_Level3 = 3 }
enum	{ preEmphasis_Disabled = 0 , preEmphasis_Level1 = 1 , preEmphasis_Level2 = 2 , preEmphasis_Level3 = 3 }
enum	{   postCursor2_Level0 = 0 , postCursor2_Level1 = 1 , postCursor2_Level2 = 2 , postCursor2_Level3 = 3 ,   postCursor2_Supported }

Functions
static int	tegra_dp_is_max_vs (u32 pe, u32 vs)
static int	tegra_dp_is_max_pe (u32 pe, u32 vs)
static int	tegra_dp_is_max_pc (u32 pc)

Variables
static const u32	tegra_dp_vs_regs [][4][4]
static const u32	tegra_dp_pe_regs [][4][4]
static const u32	tegra_dp_pc_regs [][4][4]
static const u32	tegra_dp_tx_pu [][4][4]

Macro Definition Documentation

DP_AUX_DEFER_MAX_TRIES

#define DP_AUX_DEFER_MAX_TRIES   7

Definition at line 122 of file displayport.h.

DP_AUX_MAX_BYTES

#define DP_AUX_MAX_BYTES   16

Definition at line 128 of file displayport.h.

DP_AUX_TIMEOUT_MAX_TRIES

#define DP_AUX_TIMEOUT_MAX_TRIES   2

Definition at line 123 of file displayport.h.

DP_AUX_TIMEOUT_MS

#define DP_AUX_TIMEOUT_MS   40

Definition at line 130 of file displayport.h.

DP_CLOCK_RECOVERY_MAX_TRIES

#define DP_CLOCK_RECOVERY_MAX_TRIES   7

Definition at line 125 of file displayport.h.

DP_CLOCK_RECOVERY_TOT_TRIES

#define DP_CLOCK_RECOVERY_TOT_TRIES   15

Definition at line 126 of file displayport.h.

DP_DPCP_RETRY_SLEEP_NS

#define DP_DPCP_RETRY_SLEEP_NS   400

Definition at line 131 of file displayport.h.

DP_POWER_ON_MAX_TRIES

#define DP_POWER_ON_MAX_TRIES   3

Definition at line 124 of file displayport.h.

DPAUX_DP_AUX_CONFIG

#define DPAUX_DP_AUX_CONFIG   (0x45)

Definition at line 80 of file displayport.h.

DPAUX_DP_AUXADDR

#define DPAUX_DP_AUXADDR   (0x29)

Definition at line 17 of file displayport.h.

DPAUX_DP_AUXCTL

#define DPAUX_DP_AUXCTL   (0x2d)

Definition at line 18 of file displayport.h.

DPAUX_DP_AUXCTL_CMD_AUXRD

#define DPAUX_DP_AUXCTL_CMD_AUXRD   (9 << 12)

Definition at line 30 of file displayport.h.

DPAUX_DP_AUXCTL_CMD_AUXWR

#define DPAUX_DP_AUXCTL_CMD_AUXWR   (8 << 12)

Definition at line 29 of file displayport.h.

DPAUX_DP_AUXCTL_CMD_I2CRD

#define DPAUX_DP_AUXCTL_CMD_I2CRD   (1 << 12)

Definition at line 24 of file displayport.h.

DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT

#define DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT   (2 << 12)

Definition at line 25 of file displayport.h.

DPAUX_DP_AUXCTL_CMD_I2CWR

#define DPAUX_DP_AUXCTL_CMD_I2CWR   (0 << 12)

Definition at line 23 of file displayport.h.

DPAUX_DP_AUXCTL_CMD_MASK

#define DPAUX_DP_AUXCTL_CMD_MASK   (0xf << 12)

Definition at line 22 of file displayport.h.

DPAUX_DP_AUXCTL_CMD_MOTRD

#define DPAUX_DP_AUXCTL_CMD_MOTRD   (5 << 12)

Definition at line 27 of file displayport.h.

DPAUX_DP_AUXCTL_CMD_MOTREQWSTAT

#define DPAUX_DP_AUXCTL_CMD_MOTREQWSTAT   (6 << 12)

Definition at line 28 of file displayport.h.

DPAUX_DP_AUXCTL_CMD_MOTWR

#define DPAUX_DP_AUXCTL_CMD_MOTWR   (4 << 12)

Definition at line 26 of file displayport.h.

DPAUX_DP_AUXCTL_CMD_SHIFT

#define DPAUX_DP_AUXCTL_CMD_SHIFT   (12)

Definition at line 21 of file displayport.h.

DPAUX_DP_AUXCTL_CMDLEN_FIELD

#define DPAUX_DP_AUXCTL_CMDLEN_FIELD   (0xff)

Definition at line 20 of file displayport.h.

DPAUX_DP_AUXCTL_CMDLEN_SHIFT

#define DPAUX_DP_AUXCTL_CMDLEN_SHIFT   (0)

Definition at line 19 of file displayport.h.

DPAUX_DP_AUXCTL_RST_ASSERT

#define DPAUX_DP_AUXCTL_RST_ASSERT   (1 << 31)

Definition at line 37 of file displayport.h.

DPAUX_DP_AUXCTL_RST_DEASSERT

#define DPAUX_DP_AUXCTL_RST_DEASSERT   (0 << 31)

Definition at line 36 of file displayport.h.

DPAUX_DP_AUXCTL_RST_SHIFT

#define DPAUX_DP_AUXCTL_RST_SHIFT   (31)

Definition at line 35 of file displayport.h.

DPAUX_DP_AUXCTL_TRANSACTREQ_DONE

#define DPAUX_DP_AUXCTL_TRANSACTREQ_DONE   (0 << 16)

Definition at line 33 of file displayport.h.

DPAUX_DP_AUXCTL_TRANSACTREQ_MASK

#define DPAUX_DP_AUXCTL_TRANSACTREQ_MASK   (0x1 << 16)

Definition at line 32 of file displayport.h.

DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING

#define DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING   (1 << 16)

Definition at line 34 of file displayport.h.

DPAUX_DP_AUXCTL_TRANSACTREQ_SHIFT

#define DPAUX_DP_AUXCTL_TRANSACTREQ_SHIFT   (16)

Definition at line 31 of file displayport.h.

DPAUX_DP_AUXDATA_READ_W

#define DPAUX_DP_AUXDATA_READ_W

(

i

)

(0x19 + 4*(i))

Definition at line 16 of file displayport.h.

DPAUX_DP_AUXDATA_WRITE_W

#define DPAUX_DP_AUXDATA_WRITE_W

(

i

)

(0x9 + 4*(i))

Definition at line 15 of file displayport.h.

DPAUX_DP_AUXSTAT

#define DPAUX_DP_AUXSTAT   (0x31)

Definition at line 38 of file displayport.h.

DPAUX_DP_AUXSTAT_AUXCTL_STATE_ADDRESS

#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_ADDRESS   (4 << 20)

Definition at line 48 of file displayport.h.

DPAUX_DP_AUXSTAT_AUXCTL_STATE_CLEANUP

#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_CLEANUP   (12 << 20)

Definition at line 56 of file displayport.h.

DPAUX_DP_AUXSTAT_AUXCTL_STATE_COMMAND

#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_COMMAND   (3 << 20)

Definition at line 47 of file displayport.h.

DPAUX_DP_AUXSTAT_AUXCTL_STATE_GET_M

#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_GET_M   (8 << 20)

Definition at line 52 of file displayport.h.

DPAUX_DP_AUXSTAT_AUXCTL_STATE_IDLE

#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_IDLE   (0 << 20)

Definition at line 44 of file displayport.h.

DPAUX_DP_AUXSTAT_AUXCTL_STATE_LENGTH

#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_LENGTH   (5 << 20)

Definition at line 49 of file displayport.h.

DPAUX_DP_AUXSTAT_AUXCTL_STATE_MASK

#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_MASK   (0xf << 20)

Definition at line 43 of file displayport.h.

DPAUX_DP_AUXSTAT_AUXCTL_STATE_READ1

#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_READ1   (7 << 20)

Definition at line 51 of file displayport.h.

DPAUX_DP_AUXSTAT_AUXCTL_STATE_REPLY

#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_REPLY   (11 << 20)

Definition at line 55 of file displayport.h.

DPAUX_DP_AUXSTAT_AUXCTL_STATE_SHIFT

#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_SHIFT   (20)

Definition at line 42 of file displayport.h.

DPAUX_DP_AUXSTAT_AUXCTL_STATE_START1

#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_START1   (2 << 20)

Definition at line 46 of file displayport.h.

DPAUX_DP_AUXSTAT_AUXCTL_STATE_STOP1

#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_STOP1   (9 << 20)

Definition at line 53 of file displayport.h.

DPAUX_DP_AUXSTAT_AUXCTL_STATE_STOP2

#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_STOP2   (10 << 20)

Definition at line 54 of file displayport.h.

DPAUX_DP_AUXSTAT_AUXCTL_STATE_SYNC

#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_SYNC   (1 << 20)

Definition at line 45 of file displayport.h.

DPAUX_DP_AUXSTAT_AUXCTL_STATE_WRITE1

#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_WRITE1   (6 << 20)

Definition at line 50 of file displayport.h.

DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED

#define DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED   (1 << 28)

Definition at line 41 of file displayport.h.

DPAUX_DP_AUXSTAT_HPD_STATUS_SHIFT

#define DPAUX_DP_AUXSTAT_HPD_STATUS_SHIFT   (28)

Definition at line 39 of file displayport.h.

DPAUX_DP_AUXSTAT_HPD_STATUS_UNPLUG

#define DPAUX_DP_AUXSTAT_HPD_STATUS_UNPLUG   (0 << 28)

Definition at line 40 of file displayport.h.

DPAUX_DP_AUXSTAT_NO_STOP_ERROR_NOT_PENDING

#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_NOT_PENDING   (0 << 11)

Definition at line 65 of file displayport.h.

DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING

#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING   (1 << 11)

Definition at line 66 of file displayport.h.

DPAUX_DP_AUXSTAT_NO_STOP_ERROR_SHIFT

#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_SHIFT   (11)

Definition at line 64 of file displayport.h.

DPAUX_DP_AUXSTAT_REPLY_M_MASK

#define DPAUX_DP_AUXSTAT_REPLY_M_MASK   (0xff << 0)

Definition at line 77 of file displayport.h.

DPAUX_DP_AUXSTAT_REPLY_M_SHIFT

#define DPAUX_DP_AUXSTAT_REPLY_M_SHIFT   (0)

Definition at line 76 of file displayport.h.

DPAUX_DP_AUXSTAT_REPLYTYPE_ACK

#define DPAUX_DP_AUXSTAT_REPLYTYPE_ACK   (0 << 16)

Definition at line 59 of file displayport.h.

DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER

#define DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER   (2 << 16)

Definition at line 61 of file displayport.h.

DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER

#define DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER   (8 << 16)

Definition at line 63 of file displayport.h.

DPAUX_DP_AUXSTAT_REPLYTYPE_I2CNACK

#define DPAUX_DP_AUXSTAT_REPLYTYPE_I2CNACK   (4 << 16)

Definition at line 62 of file displayport.h.

DPAUX_DP_AUXSTAT_REPLYTYPE_MASK

#define DPAUX_DP_AUXSTAT_REPLYTYPE_MASK   (0xf << 16)

Definition at line 58 of file displayport.h.

DPAUX_DP_AUXSTAT_REPLYTYPE_NACK

#define DPAUX_DP_AUXSTAT_REPLYTYPE_NACK   (1 << 16)

Definition at line 60 of file displayport.h.

DPAUX_DP_AUXSTAT_REPLYTYPE_SHIFT

#define DPAUX_DP_AUXSTAT_REPLYTYPE_SHIFT   (16)

Definition at line 57 of file displayport.h.

DPAUX_DP_AUXSTAT_RX_ERROR_NOT_PENDING

#define DPAUX_DP_AUXSTAT_RX_ERROR_NOT_PENDING   (0 << 9)

Definition at line 71 of file displayport.h.

DPAUX_DP_AUXSTAT_RX_ERROR_PENDING

#define DPAUX_DP_AUXSTAT_RX_ERROR_PENDING   (1 << 9)

Definition at line 72 of file displayport.h.

DPAUX_DP_AUXSTAT_RX_ERROR_SHIFT

#define DPAUX_DP_AUXSTAT_RX_ERROR_SHIFT   (9)

Definition at line 70 of file displayport.h.

DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_NOT_PENDING

#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_NOT_PENDING   (0 << 10)

Definition at line 68 of file displayport.h.

DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING

#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING   (1 << 10)

Definition at line 69 of file displayport.h.

DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_SHIFT

#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_SHIFT   (10)

Definition at line 67 of file displayport.h.

DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_NOT_PENDING

#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_NOT_PENDING   (0 << 8)

Definition at line 74 of file displayport.h.

DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING

#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING   (1 << 8)

Definition at line 75 of file displayport.h.

DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_SHIFT

#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_SHIFT   (8)

Definition at line 73 of file displayport.h.

DPAUX_HPD_CONFIG

#define DPAUX_HPD_CONFIG   (0x3d)

Definition at line 78 of file displayport.h.

DPAUX_HPD_CONFIG_UNPLUG_MIN_TIME_SHIFT

#define DPAUX_HPD_CONFIG_UNPLUG_MIN_TIME_SHIFT   (16)

Definition at line 116 of file displayport.h.

DPAUX_HPD_IRQ_CONFIG

#define DPAUX_HPD_IRQ_CONFIG   (0x41)

Definition at line 79 of file displayport.h.

DPAUX_HYBRID_PADCTL

#define DPAUX_HYBRID_PADCTL   (0x49)

Definition at line 81 of file displayport.h.

DPAUX_HYBRID_PADCTL_AUX_CMH_DEFAULT_MASK

#define DPAUX_HYBRID_PADCTL_AUX_CMH_DEFAULT_MASK   (0x3 << 12)

Definition at line 89 of file displayport.h.

DPAUX_HYBRID_PADCTL_AUX_CMH_SHIFT

#define DPAUX_HYBRID_PADCTL_AUX_CMH_SHIFT   (12)

Definition at line 88 of file displayport.h.

DPAUX_HYBRID_PADCTL_AUX_CMH_V0_56

#define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_56   (3 << 12)

Definition at line 93 of file displayport.h.

DPAUX_HYBRID_PADCTL_AUX_CMH_V0_60

#define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_60   (0 << 12)

Definition at line 90 of file displayport.h.

DPAUX_HYBRID_PADCTL_AUX_CMH_V0_64

#define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_64   (1 << 12)

Definition at line 91 of file displayport.h.

DPAUX_HYBRID_PADCTL_AUX_CMH_V0_70

#define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_70   (2 << 12)

Definition at line 92 of file displayport.h.

DPAUX_HYBRID_PADCTL_AUX_DRVI_DEFAULT_MASK

#define DPAUX_HYBRID_PADCTL_AUX_DRVI_DEFAULT_MASK   (0x3f << 2)

Definition at line 105 of file displayport.h.

DPAUX_HYBRID_PADCTL_AUX_DRVI_SHIFT

#define DPAUX_HYBRID_PADCTL_AUX_DRVI_SHIFT   (2)

Definition at line 104 of file displayport.h.

DPAUX_HYBRID_PADCTL_AUX_DRVZ_DEFAULT_MASK

#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_DEFAULT_MASK   (0x7 << 8)

Definition at line 95 of file displayport.h.

DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_34

#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_34   (7 << 8)

Definition at line 103 of file displayport.h.

DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_39

#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_39   (6 << 8)

Definition at line 102 of file displayport.h.

DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_42

#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_42   (5 << 8)

Definition at line 101 of file displayport.h.

DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_45

#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_45   (3 << 8)

Definition at line 99 of file displayport.h.

DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_50

#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_50   (4 << 8)

Definition at line 100 of file displayport.h.

DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_54

#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_54   (2 << 8)

Definition at line 98 of file displayport.h.

DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_60

#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_60   (1 << 8)

Definition at line 97 of file displayport.h.

DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_78

#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_78   (0 << 8)

Definition at line 96 of file displayport.h.

DPAUX_HYBRID_PADCTL_AUX_DRVZ_SHIFT

#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_SHIFT   (8)

Definition at line 94 of file displayport.h.

DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_DISABLE

#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_DISABLE   (0 << 1)

Definition at line 107 of file displayport.h.

DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_ENABLE

#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_ENABLE   (1 << 1)

Definition at line 108 of file displayport.h.

DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_SHIFT

#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_SHIFT   (1)

Definition at line 106 of file displayport.h.

DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_DISABLE

#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_DISABLE   (0 << 14)

Definition at line 86 of file displayport.h.

DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_ENABLE

#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_ENABLE   (1 << 14)

Definition at line 87 of file displayport.h.

DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_SHIFT

#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_SHIFT   (14)

Definition at line 85 of file displayport.h.

DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_DISABLE

#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_DISABLE   (0 << 15)

Definition at line 83 of file displayport.h.

DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_ENABLE

#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_ENABLE   (1 << 15)

Definition at line 84 of file displayport.h.

DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_SHIFT

#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_SHIFT   (15)

Definition at line 82 of file displayport.h.

DPAUX_HYBRID_PADCTL_MODE_AUX

#define DPAUX_HYBRID_PADCTL_MODE_AUX   (0)

Definition at line 110 of file displayport.h.

DPAUX_HYBRID_PADCTL_MODE_I2C

#define DPAUX_HYBRID_PADCTL_MODE_I2C   (1)

Definition at line 111 of file displayport.h.

DPAUX_HYBRID_PADCTL_MODE_SHIFT

#define DPAUX_HYBRID_PADCTL_MODE_SHIFT   (0)

Definition at line 109 of file displayport.h.

DPAUX_HYBRID_SPARE

#define DPAUX_HYBRID_SPARE   (0x4d)

Definition at line 112 of file displayport.h.

DPAUX_HYBRID_SPARE_PAD_PWR_POWERDOWN

#define DPAUX_HYBRID_SPARE_PAD_PWR_POWERDOWN   (1)

Definition at line 114 of file displayport.h.

DPAUX_HYBRID_SPARE_PAD_PWR_POWERUP

#define DPAUX_HYBRID_SPARE_PAD_PWR_POWERUP   (0)

Definition at line 113 of file displayport.h.

DPAUX_INTR_AUX

#define DPAUX_INTR_AUX   (0x5)

Definition at line 14 of file displayport.h.

DPAUX_INTR_EN_AUX

#define DPAUX_INTR_EN_AUX   (0x1)

Definition at line 13 of file displayport.h.

EDP_PWR_OFF_TO_ON_TIME_MS

#define EDP_PWR_OFF_TO_ON_TIME_MS   (500+10)

Definition at line 318 of file displayport.h.

EDP_PWR_ON_TO_AUX_TIME_MS

#define EDP_PWR_ON_TO_AUX_TIME_MS   (200+10)

Definition at line 313 of file displayport.h.

EDP_PWR_ON_TO_ML_TIME_MS

#define EDP_PWR_ON_TO_ML_TIME_MS   (200+10)

Definition at line 315 of file displayport.h.

NV_DPCD_ADJUST_REQ_LANEX_DC_MASK

#define NV_DPCD_ADJUST_REQ_LANEX_DC_MASK   0x3

Definition at line 435 of file displayport.h.

NV_DPCD_ADJUST_REQ_LANEX_DC_SHIFT

#define NV_DPCD_ADJUST_REQ_LANEX_DC_SHIFT   0

Definition at line 434 of file displayport.h.

NV_DPCD_ADJUST_REQ_LANEX_PE_MASK

#define NV_DPCD_ADJUST_REQ_LANEX_PE_MASK   (0x3 << 2)

Definition at line 437 of file displayport.h.

NV_DPCD_ADJUST_REQ_LANEX_PE_SHIFT

#define NV_DPCD_ADJUST_REQ_LANEX_PE_SHIFT   2

Definition at line 436 of file displayport.h.

NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_MASK

#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_MASK   (0x3 << 4)

Definition at line 439 of file displayport.h.

NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_SHIFT

#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_SHIFT   4

Definition at line 438 of file displayport.h.

NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_MASK

#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_MASK   (0x3 << 6)

Definition at line 441 of file displayport.h.

NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_SHIFT

#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_SHIFT   6

Definition at line 440 of file displayport.h.

NV_DPCD_ADJUST_REQ_POST_CURSOR2

#define NV_DPCD_ADJUST_REQ_POST_CURSOR2   (0x0000020C)

Definition at line 442 of file displayport.h.

NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_MASK

#define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_MASK   0x3

Definition at line 443 of file displayport.h.

NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_SHIFT

#define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_SHIFT

(

i

)

(i*2)

Definition at line 444 of file displayport.h.

NV_DPCD_BRANCH_IEEE_OUI

#define NV_DPCD_BRANCH_IEEE_OUI   (0x00000500)

Definition at line 448 of file displayport.h.

NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR

#define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR   (0x00000201)

Definition at line 402 of file displayport.h.

NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_AUTO_TEST_NO

#define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_AUTO_TEST_NO   (0x00000000 << 1)

Definition at line 403 of file displayport.h.

NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_AUTO_TEST_YES

#define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_AUTO_TEST_YES   (0x00000001 << 1)

Definition at line 404 of file displayport.h.

NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_CP_NO

#define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_CP_NO   (0x00000000 << 2)

Definition at line 405 of file displayport.h.

NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_CP_YES

#define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_CP_YES   (0x00000001 << 2)

Definition at line 406 of file displayport.h.

NV_DPCD_DOWNSPREAD_CTRL

#define NV_DPCD_DOWNSPREAD_CTRL   (0x00000107)

Definition at line 383 of file displayport.h.

NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_LT_0_5

#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_LT_0_5   (0x00000001 << 4)

Definition at line 385 of file displayport.h.

NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_NONE

#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_NONE   (0x00000000 << 4)

Definition at line 384 of file displayport.h.

NV_DPCD_EDP_CONFIG_CAP

#define NV_DPCD_EDP_CONFIG_CAP   (0x0000000D)

Definition at line 355 of file displayport.h.

NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_NO

#define NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_NO   (0x00000000)

Definition at line 356 of file displayport.h.

NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES

#define NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES   (0x00000001)

Definition at line 357 of file displayport.h.

NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_NO

#define NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_NO   (0x00000000 << 1)

Definition at line 358 of file displayport.h.

NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES

#define NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES   (0x00000001 << 1)

Definition at line 359 of file displayport.h.

NV_DPCD_EDP_CONFIG_SET

#define NV_DPCD_EDP_CONFIG_SET   (0x0000010A)

Definition at line 388 of file displayport.h.

NV_DPCD_EDP_CONFIG_SET_ASC_RESET_DISABLE

#define NV_DPCD_EDP_CONFIG_SET_ASC_RESET_DISABLE   (0x00000000)

Definition at line 389 of file displayport.h.

NV_DPCD_EDP_CONFIG_SET_ASC_RESET_ENABLE

#define NV_DPCD_EDP_CONFIG_SET_ASC_RESET_ENABLE   (0x00000001)

Definition at line 390 of file displayport.h.

NV_DPCD_EDP_CONFIG_SET_FRAMING_CHANGE_DISABLE

#define NV_DPCD_EDP_CONFIG_SET_FRAMING_CHANGE_DISABLE   (0x00000000 << 1)

Definition at line 391 of file displayport.h.

NV_DPCD_EDP_CONFIG_SET_FRAMING_CHANGE_ENABLE

#define NV_DPCD_EDP_CONFIG_SET_FRAMING_CHANGE_ENABLE   (0x00000001 << 1)

Definition at line 392 of file displayport.h.

NV_DPCD_HDCP_AINFO_OFFSET

#define NV_DPCD_HDCP_AINFO_OFFSET   (0x0006803B)

Definition at line 462 of file displayport.h.

NV_DPCD_HDCP_AKSV_OFFSET

#define NV_DPCD_HDCP_AKSV_OFFSET   (0x00068007)

Definition at line 455 of file displayport.h.

NV_DPCD_HDCP_AN_OFFSET

#define NV_DPCD_HDCP_AN_OFFSET   (0x0006800C)

Definition at line 456 of file displayport.h.

NV_DPCD_HDCP_BCAPS_OFFSET

#define NV_DPCD_HDCP_BCAPS_OFFSET   (0x00068028)

Definition at line 458 of file displayport.h.

NV_DPCD_HDCP_BINFO_OFFSET

#define NV_DPCD_HDCP_BINFO_OFFSET   (0x0006802A)

Definition at line 460 of file displayport.h.

NV_DPCD_HDCP_BKSV_OFFSET

#define NV_DPCD_HDCP_BKSV_OFFSET   (0x00068000)

Definition at line 453 of file displayport.h.

NV_DPCD_HDCP_BSTATUS_OFFSET

#define NV_DPCD_HDCP_BSTATUS_OFFSET   (0x00068029)

Definition at line 459 of file displayport.h.

NV_DPCD_HDCP_KSV_FIFO_OFFSET

#define NV_DPCD_HDCP_KSV_FIFO_OFFSET   (0x0006802C)

Definition at line 461 of file displayport.h.

NV_DPCD_HDCP_RPRIME_OFFSET

#define NV_DPCD_HDCP_RPRIME_OFFSET   (0x00068005)

Definition at line 454 of file displayport.h.

NV_DPCD_HDCP_VPRIME_OFFSET

#define NV_DPCD_HDCP_VPRIME_OFFSET   (0x00068014)

Definition at line 457 of file displayport.h.

NV_DPCD_LANE0_1_ADJUST_REQ

#define NV_DPCD_LANE0_1_ADJUST_REQ   (0x00000206)

Definition at line 432 of file displayport.h.

NV_DPCD_LANE0_1_STATUS

#define NV_DPCD_LANE0_1_STATUS   (0x00000202)

Definition at line 407 of file displayport.h.

NV_DPCD_LANE2_3_ADJUST_REQ

#define NV_DPCD_LANE2_3_ADJUST_REQ   (0x00000207)

Definition at line 433 of file displayport.h.

NV_DPCD_LANE2_3_STATUS

#define NV_DPCD_LANE2_3_STATUS   (0x00000203)

Definition at line 408 of file displayport.h.

NV_DPCD_LANE_ALIGN_STATUS_UPDATED

#define NV_DPCD_LANE_ALIGN_STATUS_UPDATED   (0x00000204)

Definition at line 427 of file displayport.h.

NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_NO

#define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_NO   (0x00000000)

Definition at line 428 of file displayport.h.

NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_YES

#define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_YES   (0x00000001)

Definition at line 429 of file displayport.h.

NV_DPCD_LANE_COUNT_SET

#define NV_DPCD_LANE_COUNT_SET   (0x00000101)

Definition at line 362 of file displayport.h.

NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_F

#define NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_F   (0x00000000 << 7)

Definition at line 363 of file displayport.h.

NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_T

#define NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_T   (0x00000001 << 7)

Definition at line 364 of file displayport.h.

NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_F

#define NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_F   (0x00000000 << 2)

Definition at line 397 of file displayport.h.

NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_T

#define NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_T   (0x00000001 << 2)

Definition at line 396 of file displayport.h.

NV_DPCD_LANEX_SET2_PC2_SHIFT

#define NV_DPCD_LANEX_SET2_PC2_SHIFT   0

Definition at line 395 of file displayport.h.

NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_F

#define NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_F   (0x00000000 << 6)

Definition at line 400 of file displayport.h.

NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_T

#define NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_T   (0x00000001 << 6)

Definition at line 399 of file displayport.h.

NV_DPCD_LANEXPLUS1_SET2_PC2_SHIFT

#define NV_DPCD_LANEXPLUS1_SET2_PC2_SHIFT   4

Definition at line 398 of file displayport.h.

NV_DPCD_LINK_BANDWIDTH_SET

#define NV_DPCD_LINK_BANDWIDTH_SET   (0x00000100)

Definition at line 361 of file displayport.h.

NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET

#define NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET   (0x00000108)

Definition at line 386 of file displayport.h.

NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET_ANSI_8B10B

#define NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET_ANSI_8B10B   1

Definition at line 387 of file displayport.h.

NV_DPCD_MAX_DOWNSPREAD

#define NV_DPCD_MAX_DOWNSPREAD   (0x00000003)

Definition at line 350 of file displayport.h.

NV_DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_F

#define NV_DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_F   (0x00000000 << 6)

Definition at line 353 of file displayport.h.

NV_DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_T

#define NV_DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_T   (0x00000001 << 6)

Definition at line 354 of file displayport.h.

NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT

#define NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT   (0x00000001)

Definition at line 352 of file displayport.h.

NV_DPCD_MAX_DOWNSPREAD_VAL_NONE

#define NV_DPCD_MAX_DOWNSPREAD_VAL_NONE   (0x00000000)

Definition at line 351 of file displayport.h.

NV_DPCD_MAX_LANE_COUNT

#define NV_DPCD_MAX_LANE_COUNT   (0x00000002)

Definition at line 342 of file displayport.h.

NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_NO

#define NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_NO   (0x00000000 << 7)

Definition at line 348 of file displayport.h.

NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES

#define NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES   (0x00000001 << 7)

Definition at line 349 of file displayport.h.

NV_DPCD_MAX_LANE_COUNT_LANE_1

#define NV_DPCD_MAX_LANE_COUNT_LANE_1   (0x00000001)

Definition at line 344 of file displayport.h.

NV_DPCD_MAX_LANE_COUNT_LANE_2

#define NV_DPCD_MAX_LANE_COUNT_LANE_2   (0x00000002)

Definition at line 345 of file displayport.h.

NV_DPCD_MAX_LANE_COUNT_LANE_4

#define NV_DPCD_MAX_LANE_COUNT_LANE_4   (0x00000004)

Definition at line 346 of file displayport.h.

NV_DPCD_MAX_LANE_COUNT_MASK

#define NV_DPCD_MAX_LANE_COUNT_MASK   (0x1f)

Definition at line 343 of file displayport.h.

NV_DPCD_MAX_LANE_COUNT_TPS3_SUPPORTED_YES

#define NV_DPCD_MAX_LANE_COUNT_TPS3_SUPPORTED_YES   (0x00000001 << 6)

Definition at line 347 of file displayport.h.

NV_DPCD_MAX_LINK_BANDWIDTH

#define NV_DPCD_MAX_LINK_BANDWIDTH   (0x00000001)

Definition at line 338 of file displayport.h.

NV_DPCD_MAX_LINK_BANDWIDTH_VAL_1_62_GPBS

#define NV_DPCD_MAX_LINK_BANDWIDTH_VAL_1_62_GPBS   (0x00000006)

Definition at line 339 of file displayport.h.

NV_DPCD_MAX_LINK_BANDWIDTH_VAL_2_70_GPBS

#define NV_DPCD_MAX_LINK_BANDWIDTH_VAL_2_70_GPBS   (0x0000000a)

Definition at line 340 of file displayport.h.

NV_DPCD_MAX_LINK_BANDWIDTH_VAL_5_40_GPBS

#define NV_DPCD_MAX_LINK_BANDWIDTH_VAL_5_40_GPBS   (0x00000014)

Definition at line 341 of file displayport.h.

NV_DPCD_REV

#define NV_DPCD_REV   (0x00000000)

Definition at line 333 of file displayport.h.

NV_DPCD_REV_MAJOR_MASK

#define NV_DPCD_REV_MAJOR_MASK   (0xf << 4)

Definition at line 335 of file displayport.h.

NV_DPCD_REV_MAJOR_SHIFT

#define NV_DPCD_REV_MAJOR_SHIFT   (4)

Definition at line 334 of file displayport.h.

NV_DPCD_REV_MINOR_MASK

#define NV_DPCD_REV_MINOR_MASK   (0xf)

Definition at line 337 of file displayport.h.

NV_DPCD_REV_MINOR_SHIFT

#define NV_DPCD_REV_MINOR_SHIFT   (0)

Definition at line 336 of file displayport.h.

NV_DPCD_SET_POWER

#define NV_DPCD_SET_POWER   (0x00000600)

Definition at line 449 of file displayport.h.

NV_DPCD_SET_POWER_VAL_D0_NORMAL

#define NV_DPCD_SET_POWER_VAL_D0_NORMAL   (0x00000001)

Definition at line 451 of file displayport.h.

NV_DPCD_SET_POWER_VAL_D3_PWRDWN

#define NV_DPCD_SET_POWER_VAL_D3_PWRDWN   (0x00000002)

Definition at line 452 of file displayport.h.

NV_DPCD_SET_POWER_VAL_RESERVED

#define NV_DPCD_SET_POWER_VAL_RESERVED   (0x00000000)

Definition at line 450 of file displayport.h.

NV_DPCD_SINK_COUNT

#define NV_DPCD_SINK_COUNT   (0x00000200)

Definition at line 401 of file displayport.h.

NV_DPCD_SINK_IEEE_OUI

#define NV_DPCD_SINK_IEEE_OUI   (0x00000400)

Definition at line 447 of file displayport.h.

NV_DPCD_SINK_STATUS

#define NV_DPCD_SINK_STATUS   (0x00000205)

Definition at line 430 of file displayport.h.

NV_DPCD_SINK_STATUS_PORT0_IN_SYNC

#define NV_DPCD_SINK_STATUS_PORT0_IN_SYNC   (0x1 << 0)

Definition at line 431 of file displayport.h.

NV_DPCD_SOURCE_IEEE_OUI

#define NV_DPCD_SOURCE_IEEE_OUI   (0x00000300)

Definition at line 446 of file displayport.h.

NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_NO

#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_NO   (0x00000000 << 1)

Definition at line 413 of file displayport.h.

NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT

#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT   1

Definition at line 412 of file displayport.h.

NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_YES

#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_YES   (0x00000001 << 1)

Definition at line 414 of file displayport.h.

NV_DPCD_STATUS_LANEX_CR_DONE_NO

#define NV_DPCD_STATUS_LANEX_CR_DONE_NO   (0x00000000)

Definition at line 410 of file displayport.h.

NV_DPCD_STATUS_LANEX_CR_DONE_SHIFT

#define NV_DPCD_STATUS_LANEX_CR_DONE_SHIFT   0

Definition at line 409 of file displayport.h.

NV_DPCD_STATUS_LANEX_CR_DONE_YES

#define NV_DPCD_STATUS_LANEX_CR_DONE_YES   (0x00000001)

Definition at line 411 of file displayport.h.

NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_NO

#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_NO   (0x00000000 << 2)

Definition at line 416 of file displayport.h.

NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT

#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT   2

Definition at line 415 of file displayport.h.

NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_YES

#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_YES   (0x00000001 << 2)

Definition at line 417 of file displayport.h.

NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_NO

#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_NO   (0x00000000 << 5)

Definition at line 422 of file displayport.h.

NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_SHIFT

#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_SHIFT   5

Definition at line 421 of file displayport.h.

NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES

#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES   (0x00000001 << 5)

Definition at line 423 of file displayport.h.

NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_NO

#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_NO   (0x00000000 << 4)

Definition at line 419 of file displayport.h.

NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_SHIFT

#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_SHIFT   4

Definition at line 418 of file displayport.h.

NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES

#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES   (0x00000001 << 4)

Definition at line 420 of file displayport.h.

NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_NO

#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_NO   (0x00000000 << 6)

Definition at line 425 of file displayport.h.

NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_SHIFT

#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_SHIFT   6

Definition at line 424 of file displayport.h.

NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES

#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES   (0x00000001 << 6)

Definition at line 426 of file displayport.h.

NV_DPCD_TEST_REQUEST

#define NV_DPCD_TEST_REQUEST   (0x00000218)

Definition at line 445 of file displayport.h.

NV_DPCD_TRAINING_AUX_RD_INTERVAL

#define NV_DPCD_TRAINING_AUX_RD_INTERVAL   (0x0000000E)

Definition at line 360 of file displayport.h.

NV_DPCD_TRAINING_LANE0_1_SET2

#define NV_DPCD_TRAINING_LANE0_1_SET2   (0x0000010F)

Definition at line 393 of file displayport.h.

NV_DPCD_TRAINING_LANE0_SET

#define NV_DPCD_TRAINING_LANE0_SET   (0x00000103)

Definition at line 373 of file displayport.h.

NV_DPCD_TRAINING_LANE1_SET

#define NV_DPCD_TRAINING_LANE1_SET   (0x00000104)

Definition at line 374 of file displayport.h.

NV_DPCD_TRAINING_LANE2_3_SET2

#define NV_DPCD_TRAINING_LANE2_3_SET2   (0x00000110)

Definition at line 394 of file displayport.h.

NV_DPCD_TRAINING_LANE2_SET

#define NV_DPCD_TRAINING_LANE2_SET   (0x00000105)

Definition at line 375 of file displayport.h.

NV_DPCD_TRAINING_LANE3_SET

#define NV_DPCD_TRAINING_LANE3_SET   (0x00000106)

Definition at line 376 of file displayport.h.

NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_F

#define NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_F   (0x00000000 << 2)

Definition at line 379 of file displayport.h.

NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_T

#define NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_T   (0x00000001 << 2)

Definition at line 378 of file displayport.h.

NV_DPCD_TRAINING_LANEX_SET_DC_SHIFT

#define NV_DPCD_TRAINING_LANEX_SET_DC_SHIFT   0

Definition at line 377 of file displayport.h.

NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_F

#define NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_F   (0x00000000 << 5)

Definition at line 382 of file displayport.h.

NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_T

#define NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_T   (0x00000001 << 5)

Definition at line 381 of file displayport.h.

NV_DPCD_TRAINING_LANEX_SET_PE_SHIFT

#define NV_DPCD_TRAINING_LANEX_SET_PE_SHIFT   3

Definition at line 380 of file displayport.h.

NV_DPCD_TRAINING_PATTERN_SET

#define NV_DPCD_TRAINING_PATTERN_SET   (0x00000102)

Definition at line 365 of file displayport.h.

NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_F

#define NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_F   (0x00000000 << 5)

Definition at line 371 of file displayport.h.

NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_T

#define NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_T   (0x00000001 << 5)

Definition at line 372 of file displayport.h.

NV_DPCD_TRAINING_PATTERN_SET_TPS_MASK

#define NV_DPCD_TRAINING_PATTERN_SET_TPS_MASK   0x3

Definition at line 366 of file displayport.h.

NV_DPCD_TRAINING_PATTERN_SET_TPS_NONE

#define NV_DPCD_TRAINING_PATTERN_SET_TPS_NONE   (0x00000000)

Definition at line 367 of file displayport.h.

NV_DPCD_TRAINING_PATTERN_SET_TPS_TP1

#define NV_DPCD_TRAINING_PATTERN_SET_TPS_TP1   (0x00000001)

Definition at line 368 of file displayport.h.

NV_DPCD_TRAINING_PATTERN_SET_TPS_TP2

#define NV_DPCD_TRAINING_PATTERN_SET_TPS_TP2   (0x00000002)

Definition at line 369 of file displayport.h.

NV_DPCD_TRAINING_PATTERN_SET_TPS_TP3

#define NV_DPCD_TRAINING_PATTERN_SET_TPS_TP3   (0x00000003)

Definition at line 370 of file displayport.h.

Enumeration Type Documentation

anonymous enum

anonymous enum

Enumerator
driveCurrent_Level0
driveCurrent_Level1
driveCurrent_Level2
driveCurrent_Level3

Definition at line 273 of file displayport.h.

anonymous enum

anonymous enum

Enumerator
preEmphasis_Disabled
preEmphasis_Level1
preEmphasis_Level2
preEmphasis_Level3

Definition at line 280 of file displayport.h.

anonymous enum

anonymous enum

Enumerator
postCursor2_Level0
postCursor2_Level1
postCursor2_Level2
postCursor2_Level3
postCursor2_Supported

Definition at line 287 of file displayport.h.

Function Documentation

tegra_dp_is_max_pc()

static int tegra_dp_is_max_pc ( u32  pc )

inlinestatic

Definition at line 305 of file displayport.h.

References postCursor2_Level3.

Referenced by tegra_dp_lt_config().

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tegra_dp_is_max_pe()

static int tegra_dp_is_max_pe ( u32  pe, u32  vs  )

inlinestatic

Definition at line 300 of file displayport.h.

References preEmphasis_Level3.

Referenced by tegra_dp_lt_config().

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tegra_dp_is_max_vs()

static int tegra_dp_is_max_vs ( u32  pe, u32  vs  )

inlinestatic

Definition at line 295 of file displayport.h.

References driveCurrent_Level3.

Referenced by tegra_dp_lt_config().

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Variable Documentation

tegra_dp_pc_regs

const u32 tegra_dp_pc_regs[][4][4]

static

Definition at line 203 of file displayport.h.

Referenced by tegra_dp_lt_config().

tegra_dp_pe_regs

const u32 tegra_dp_pe_regs[][4][4]

static

Definition at line 168 of file displayport.h.

Referenced by tegra_dp_lt_config().

tegra_dp_tx_pu

const u32 tegra_dp_tx_pu[][4][4]

static

Definition at line 238 of file displayport.h.

tegra_dp_vs_regs

const u32 tegra_dp_vs_regs[][4][4]

static

Definition at line 133 of file displayport.h.

Referenced by tegra_dp_lt_config().