coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
ptt.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <soc/pci_devs.h>
4 #include <device/pci_ops.h>
5 #include <console/console.h>
6 
7 #include "ptt.h"
8 
9 #define PCI_ME_HFSTS4 0x64
10 #define PTT_ENABLE (1 << 19)
11 
12 /* Dump Intel ME register */
13 static uint32_t read_register(int reg_addr)
14 {
15  if (!PCH_DEV_CSE)
16  return 0xFFFFFFFF;
17 
18  return pci_read_config32(PCH_DEV_CSE, reg_addr);
19 }
20 
21 /*
22  * ptt_active()
23  *
24  * Check if PTT Flag is set - so that PTT is active.
25  *
26  * Return true if active, false otherwise.
27  */
28 bool ptt_active(void)
29 {
31 
32  if (fwsts4 == 0xFFFFFFFF)
33  return false;
34 
35  if ((fwsts4 & PTT_ENABLE) == 0) {
36  printk(BIOS_DEBUG, "Intel ME Establishment bit not valid.\n");
37  return false;
38  }
39 
40  return true;
41 }
#define printk(level,...)
Definition: stdlib.h:16
static __always_inline u32 pci_read_config32(const struct device *dev, u16 reg)
Definition: pci_ops.h:58
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
Definition: loglevel.h:128
#define PTT_ENABLE
Definition: ptt.c:10
#define PCI_ME_HFSTS4
Definition: ptt.c:9
bool ptt_active(void)
Definition: ptt.c:28
static uint32_t read_register(int reg_addr)
Definition: ptt.c:13
#define PCH_DEV_CSE
Definition: pci_devs.h:150
unsigned int uint32_t
Definition: stdint.h:14