coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
xhci.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 /* TODO: Check if this is still correct */
4 
5 #include <amdblocks/gpio.h>
6 #include <amdblocks/smi.h>
7 #include <bootstate.h>
8 #include <device/device.h>
9 #include <device/pci_ids.h>
11 #include <soc/pci_devs.h>
12 #include <soc/smi.h>
13 
14 static const struct sci_source xhci_sci_sources[] = {
15  {
17  .gpe = GEVENT_31,
18  .direction = SMI_SCI_LVL_HIGH,
19  .level = SMI_SCI_EDG
20  },
21  {
22  .scimap = SMITYPE_XHC1_PME,
23  .gpe = GEVENT_31,
24  .direction = SMI_SCI_LVL_HIGH,
25  .level = SMI_SCI_EDG
26  },
27  {
28  .scimap = SMITYPE_XHC2_PME,
29  .gpe = GEVENT_31,
30  .direction = SMI_SCI_LVL_HIGH,
31  .level = SMI_SCI_EDG
32  }
33 };
34 
35 enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe)
36 {
37  if (dev->bus->dev->path.type != DEVICE_PATH_PCI)
38  return CB_ERR_ARG;
39 
40  if (dev->path.type != DEVICE_PATH_PCI)
41  return CB_ERR_ARG;
42 
43  if (dev->bus->dev->path.pci.devfn == PCIE_ABC_A_DEVFN) {
44  if (dev->path.pci.devfn == XHCI0_DEVFN) {
45  *gpe = xhci_sci_sources[0].gpe;
46  return CB_SUCCESS;
47  } else if (dev->path.pci.devfn == XHCI1_DEVFN) {
48  *gpe = xhci_sci_sources[1].gpe;
49  return CB_SUCCESS;
50  }
51  } else if (dev->bus->dev->path.pci.devfn == PCIE_GPP_C_DEVFN) {
52  if (dev->path.pci.devfn == XHCI2_DEVFN
54  *gpe = xhci_sci_sources[2].gpe;
55  return CB_SUCCESS;
56  }
57  }
58 
59  return CB_ERR_ARG;
60 }
61 
62 static void configure_xhci_sci(void *unused)
63 {
64  const struct device *xhci_2 = DEV_PTR(xhci_2);
67  else
69 }
70 
@ BS_POST_DEVICE
Definition: bootstate.h:84
@ BS_ON_ENTRY
Definition: bootstate.h:95
#define ARRAY_SIZE(a)
Definition: helpers.h:12
cb_err
coreboot error codes
Definition: cb_err.h:15
@ CB_ERR_ARG
Invalid argument.
Definition: cb_err.h:18
@ CB_SUCCESS
Call completed successfully.
Definition: cb_err.h:16
#define DEV_PTR(_alias)
Definition: device.h:403
@ DEVICE_PATH_PCI
Definition: path.h:9
#define PCI_DID_AMD_FAM17H_MODELA0H_XHCI2
Definition: pci_ids.h:602
#define PCIE_GPP_C_DEVFN
Definition: pci_devs.h:111
#define XHCI1_DEVFN
Definition: pci_devs.h:88
#define PCIE_ABC_A_DEVFN
Definition: pci_devs.h:71
#define XHCI0_DEVFN
Definition: pci_devs.h:84
#define SMITYPE_XHC1_PME
Definition: smi.h:103
#define SMITYPE_XHC0_PME
Definition: smi.h:102
BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, configure_xhci_sci, NULL)
enum cb_err pci_xhci_get_wake_gpe(const struct device *dev, int *gpe)
Definition: xhci.c:26
#define GEVENT_31
Definition: gpio_defs.h:297
@ SMI_SCI_EDG
Definition: smi.h:28
@ SMI_SCI_LVL_HIGH
Definition: smi.h:24
void gpe_configure_sci(const struct sci_source *scis, size_t num_gpes)
Definition: smi_util.c:116
#define XHCI2_DEVFN
Definition: pci_devs.h:92
#define SMITYPE_XHC2_PME
Definition: smi.h:88
static const struct sci_source xhci_sci_sources[]
Definition: xhci.c:14
static void configure_xhci_sci(void *unused)
Definition: xhci.c:62
#define NULL
Definition: stddef.h:19
DEVTREE_CONST struct device * dev
Definition: device.h:78
struct pci_path pci
Definition: path.h:116
enum device_path_type type
Definition: path.h:114
Definition: device.h:107
struct device_path path
Definition: device.h:115
DEVTREE_CONST struct bus * bus
Definition: device.h:108
unsigned int device
Definition: device.h:117
unsigned int devfn
Definition: path.h:54
Definition: smi.h:37
uint8_t gpe
Definition: smi.h:39
uint8_t scimap
Definition: smi.h:38