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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Go to the source code of this file.
Data Structures | |
| struct | flash_ctrlr |
| struct | spi_context |
Macros | |
| #define | SPISTS 0x3020 /* Status register */ |
| #define | SPICTL 0x3022 /* Control register */ |
| #define | SPIADDR 0x3024 /* Flash chip select and 24-bit address */ |
| #define | SPIDATA 0x3028 /* 64-byte send/receive data buffer */ |
| #define | SPIBBAR 0x3070 /* BIOS base address */ |
| #define | SPIPREOP 0x3074 /* Prefix opcode table */ |
| #define | SPITYPE 0x3076 /* Opcode type table */ |
| #define | SPIOPMENU 0x3078 /* Opcode table */ |
| #define | SPIPBR0 0x3080 /* Protected BIOS range */ |
| #define | SPIPBR1 0x3084 |
| #define | SPIPBR2 0x3088 |
| #define | SPISTS_CLD 0x8000 /* Lock SPI controller configuration */ |
| #define | SPISTS_BA 0x0008 /* Access is blocked */ |
| #define | SPISTS_CD 0x0004 /* Cycle done */ |
| #define | SPISTS_CIP 0x0001 /* Cycle in progress */ |
| #define | SPICTL_SMIEN 0x8000 /* Assert SMI_B at cycle done */ |
| #define | SPICTL_DC 0x4000 /* Cycle contains data */ |
| #define | SPICTL_DBCNT 0x3f00 /* Data byte count - 1, 1 - 64 bytes */ |
| #define | SPICTL_DBCNT_SHIFT 8 |
| #define | SPICTL_COPTR 0x0070 /* Opcode menu index, 0 - 7 */ |
| #define | SPICTL_COPTR_SHIFT 4 |
| #define | SPICTL_SOPTR 0x0008 /* Prefix index, 0 - 1 */ |
| #define | SPICTL_SOPTR_SHIFT 3 |
| #define | SPICTL_ACS 0x0004 /* Atomic cycle sequence */ |
| #define | SPICTL_CG 0x0002 /* Cycle go */ |
| #define | SPICTL_AR 0x0001 /* Access request */ |
| #define | SPITYPE_ADDRESS 0x0002 /* 3-byte address required */ |
| #define | SPITYPE_PREFIX 0x0001 /* Prefix required, write/erase cycle */ |
| #define | SPIPBR_WPE 0x80000000 /* Write protect enable */ |
| #define | SPIPBR_PRL 0x00fff000 /* Protected range limit */ |
| #define | SPIPBR_PRB_SHIFT 12 |
| #define | SPIPBR_PRB 0x00000fff /* Protected range base */ |
Functions | |
| void | spi_bios_base (uint32_t bios_base_address) |
| void | spi_controller_lock (void) |
| void | spi_display (volatile struct flash_ctrlr *ctrlr) |
| const char * | spi_opcode_name (int opcode) |
| int | spi_protection (uint32_t address, uint32_t length) |
Variables | |
| const struct spi_ctrlr | spi_driver |
| #define SPICTL_DBCNT 0x3f00 /* Data byte count - 1, 1 - 64 bytes */ |
| #define SPISTS_CLD 0x8000 /* Lock SPI controller configuration */ |
| #define SPITYPE_PREFIX 0x0001 /* Prefix required, write/erase cycle */ |
Definition at line 21 of file spi.c.
References address, flash_ctrlr::bbar, spi_context::ctrlr, and spi_driver_context.
Definition at line 31 of file spi.c.
References spi_context::ctrlr, spi_driver_context, SPISTS_CLD, and flash_ctrlr::status.
| void spi_display | ( | volatile struct flash_ctrlr * | ctrlr | ) |
Definition at line 48 of file spi_debug.c.
References ARRAY_SIZE, flash_ctrlr::bbar, BIOS_DEBUG, flash_ctrlr::opmenu, flash_ctrlr::pbr, flash_ctrlr::prefix, printk, spi_opcode_name(), SPIPBR_PRB, SPIPBR_PRB_SHIFT, SPIPBR_PRL, SPIPBR_WPE, SPISTS_CLD, SPITYPE_ADDRESS, SPITYPE_PREFIX, flash_ctrlr::status, type, and flash_ctrlr::type.
| const char* spi_opcode_name | ( | int | opcode | ) |
Definition at line 6 of file spi_debug.c.
Referenced by spi_display().
Definition at line 39 of file spi.c.
References address, ARRAY_SIZE, base, BIOS_ERR, spi_context::ctrlr, length, flash_ctrlr::pbr, printk, read32(), spi_driver_context, SPIPBR_PRB, SPIPBR_PRB_SHIFT, SPIPBR_PRL, SPIPBR_WPE, value, and write32().
1.9.1