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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/lynxpoint/pch.h>
Go to the source code of this file.
Functions | |
void | mainboard_config_rcba (void) |
void | mb_get_spd_map (struct spd_info *spdi) |
Variables | |
const struct usb2_port_config | mainboard_usb2_ports [MAX_USB2_PORTS] |
const struct usb3_port_config | mainboard_usb3_ports [MAX_USB3_PORTS] |
Definition at line 7 of file romstage.c.
References D22IP, D22IP_MEI1IP, D22IR, D25IP, D25IP_LIP, D25IR, D26IP, D26IP_E2P, D26IR, D27IP, D27IP_ZIP, D27IR, D28IP, D28IP_P1IP, D28IP_P3IP, D28IP_P4IP, D28IR, D29IP, D29IP_E1P, D29IR, D30IP, D30IP_PIP, D31IP, D31IP_SIP, D31IP_SIP2, D31IP_SMIP, D31IP_TTIP, D31IR, DIR_ROUTE, INTA, INTB, INTC, NOINT, PIRQA, PIRQB, PIRQC, PIRQD, PIRQE, PIRQF, PIRQG, PIRQH, RCBA16, and RCBA32.
Definition at line 43 of file romstage.c.
const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] |
Definition at line 43 of file romstage.c.
const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] |
Definition at line 43 of file romstage.c.