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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <delay.h>
#include <stdlib.h>
#include <stdint.h>
#include <string.h>
#include <arch/io.h>
#include <device/mmio.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
Go to the source code of this file.
Data Structures | |
struct | firmware |
struct | drm_device |
Macros | |
#define | __iomem |
#define | pci_dev device |
#define | SZ_16M 0x01000000 |
#define | min_t(type, x, y) |
#define | dev_info(dev, format, arg...) printk(BIOS_INFO, "%s: " format, __func__, ##arg) |
#define | dev_dbg(dev, format, arg...) printk(BIOS_DEBUG, "%s: " format, __func__, ##arg) |
#define | dev_err(dev, format, arg...) printk(BIOS_ERR, "%s: " format, __func__, ##arg) |
#define | pr_info(format, arg...) printk(BIOS_INFO, "%s: " format, __func__, ##arg) |
#define | pr_debug(format, arg...) printk(BIOS_INFO, "%s: " format, __func__, ##arg) |
#define | pr_err(format, arg...) printk(BIOS_ERR, "%s: " format, __func__, ##arg) |
#define | DRM_INFO pr_info |
#define | GFP_KERNEL 0 |
#define | GFP_ATOMIC 1 |
#define | kfree(address) free(address) |
#define | EIO 5 |
#define | ENOMEM 12 |
Typedefs | |
typedef u64 | phys_addr_t |
#define __iomem |
Definition at line 19 of file aspeed_coreboot.h.
#define dev_dbg | ( | dev, | |
format, | |||
arg... | |||
) | printk(BIOS_DEBUG, "%s: " format, __func__, ##arg) |
Definition at line 31 of file aspeed_coreboot.h.
Definition at line 32 of file aspeed_coreboot.h.
Definition at line 30 of file aspeed_coreboot.h.
#define DRM_INFO pr_info |
Definition at line 38 of file aspeed_coreboot.h.
#define EIO 5 |
Definition at line 44 of file aspeed_coreboot.h.
#define ENOMEM 12 |
Definition at line 45 of file aspeed_coreboot.h.
#define GFP_ATOMIC 1 |
Definition at line 41 of file aspeed_coreboot.h.
#define GFP_KERNEL 0 |
Definition at line 40 of file aspeed_coreboot.h.
Definition at line 42 of file aspeed_coreboot.h.
Definition at line 25 of file aspeed_coreboot.h.
#define pci_dev device |
Definition at line 21 of file aspeed_coreboot.h.
Definition at line 35 of file aspeed_coreboot.h.
Definition at line 36 of file aspeed_coreboot.h.
Definition at line 34 of file aspeed_coreboot.h.
#define SZ_16M 0x01000000 |
Definition at line 23 of file aspeed_coreboot.h.
typedef u64 phys_addr_t |
Definition at line 20 of file aspeed_coreboot.h.
Definition at line 124 of file aspeed_coreboot.h.
References read16().
Definition at line 116 of file aspeed_coreboot.h.
References read32().
Definition at line 132 of file aspeed_coreboot.h.
References read8().
Definition at line 148 of file aspeed_coreboot.h.
References inw().
Definition at line 140 of file aspeed_coreboot.h.
References inl().
Definition at line 156 of file aspeed_coreboot.h.
References inb().
Definition at line 128 of file aspeed_coreboot.h.
References val, and write16().
Definition at line 120 of file aspeed_coreboot.h.
References val, and write32().
Definition at line 61 of file aspeed_coreboot.h.
References malloc(), and memset().
Referenced by ast_detect_chip(), and ast_driver_load().
Definition at line 164 of file aspeed_coreboot.h.
References udelay().
Referenced by ast_set_dp501_video_output().
Definition at line 81 of file aspeed_coreboot.h.
References pci_read_config8(), and val.
Definition at line 67 of file aspeed_coreboot.h.
References pci_read_config32(), and val.
Referenced by ast_detect_chip(), ast_post_gpu(), and ast_set_def_ext_reg().
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inlinestatic |
Definition at line 100 of file aspeed_coreboot.h.
References resource_at_bar(), and resource::size.
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inlinestatic |
Definition at line 108 of file aspeed_coreboot.h.
References resource::base, and resource_at_bar().
Definition at line 74 of file aspeed_coreboot.h.
References pci_write_config32(), and val.
Referenced by ast_post_gpu().
Definition at line 88 of file aspeed_coreboot.h.
References resource::next, and NULL.
Referenced by pci_resource_len(), and pci_resource_start().