16 ast_io_write8(
ast,
base, index);
25 ast_io_write8(
ast,
base, index);
26 ret = ast_io_read8(
ast,
base + 1);
34 ast_io_write8(
ast,
base, index);
46 *scu_rev = 0xffffffff;
59 if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) {
61 data = ast_read32(
ast, 0xf004);
62 if (data != 0xFFFFFFFF) {
66 DRM_INFO(
"Using P2A bridge for configuration\n");
69 ast_write32(
ast, 0xf004, 0x1e6e0000);
70 ast_write32(
ast, 0xf000, 0x1);
71 *scu_rev = ast_read32(
ast, 0x1207c);
77 DRM_INFO(
"P2A bridge disabled, using default configuration\n");
93 DRM_INFO(
"VGA not enabled on entry, requesting chip POST\n");
113 uint8_t revision = data & 0xff;
114 if (revision >= 0x40) {
117 }
else if (revision >= 0x30) {
120 }
else if (revision >= 0x20) {
123 }
else if (revision >= 0x10) {
124 switch (scu_rev & 0x0300) {
161 else if (jreg & 0x01)
166 (scu_rev & 0x300) == 0x0)
169 (scu_rev & 0x300) == 0x100)
224 DRM_INFO(
"Using Sil164 TMDS transmitter\n");
227 DRM_INFO(
"Using DP501 DisplayPort transmitter\n");
238 uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap;
239 uint32_t denum, num, div, ref_pll, dsel;
247 mcr_cfg = 0x00000577;
248 mcr_scu_mpll = 0x000050C0;
252 ast_write32(
ast, 0xf004, 0x1e6e0000);
253 ast_write32(
ast, 0xf000, 0x1);
254 mcr_cfg = ast_read32(
ast, 0x10004);
255 mcr_scu_mpll = ast_read32(
ast, 0x10120);
256 mcr_scu_strap = ast_read32(
ast, 0x10170);
275 switch (mcr_cfg & 0x03) {
291 switch (mcr_cfg & 0x03) {
307 switch (mcr_cfg & 0x0c) {
324 if (mcr_scu_strap & 0x2000)
329 denum = mcr_scu_mpll & 0x1f;
330 num = (mcr_scu_mpll & 0x3fe0) >> 5;
331 dsel = (mcr_scu_mpll & 0xc000) >> 14;
344 ast->
mclk = ref_pll * (num + 2) / (denum + 2) * (div * 1000);
365 switch (jreg & 0x03) {
419 DRM_INFO(
"platform has no IO space, trying MMIO\n");
443 DRM_INFO(
"dram MCLK=%u Mhz type=%d bus_width=%d size=%08x\n",
static int pci_read_config_dword(struct pci_dev *dev, int where, u32 *val)
#define dev_err(dev, format, arg...)
static void * kzalloc(size_t size, int flags)
bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size)
#define AST_VIDMEM_SIZE_8M
void ast_post_gpu(struct drm_device *dev)
#define AST_VIDMEM_SIZE_16M
void ast_enable_mmio(struct drm_device *dev)
static void ast_set_index_reg(struct ast_private *ast, uint32_t base, uint8_t index, uint8_t val)
void ast_enable_vga(struct drm_device *dev)
bool ast_is_vga_enabled(struct drm_device *dev)
#define AST_VIDMEM_SIZE_32M
#define AST_VIDMEM_SIZE_64M
static void ast_open_key(struct ast_private *ast)
#define AST_VIDMEM_DEFAULT_SIZE
static struct ast_private * ast
uint8_t ast_get_index_reg_mask(struct ast_private *ast, uint32_t base, uint8_t index, uint8_t mask)
static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev)
static int ast_get_dram_info(struct drm_device *dev)
void ast_set_index_reg_mask(struct ast_private *ast, uint32_t base, uint8_t index, uint8_t mask, uint8_t val)
static u32 ast_get_vram_info(struct drm_device *dev)
int ast_driver_load(struct drm_device *dev, unsigned long flags)
uint8_t ast_get_index_reg(struct ast_private *ast, uint32_t base, uint8_t index)
static int ast_detect_chip(struct drm_device *dev, bool *need_post)
struct resource * probe_resource(const struct device *dev, unsigned int index)
See if a resource structure already exists for a given index.
#define PCI_BASE_ADDRESS_2
#define PCI_BASE_ADDRESS_1
static void * res2mmio(const struct resource *res, unsigned long offset, unsigned long mask)
enum ast_private::@25 config_mode
enum ast_tx_chip tx_chip_type