4 #include <PlatformMemoryConfiguration.h>
8 static const PCIe_PORT_DESCRIPTOR
PortList[] = {
12 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4),
13 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4,
22 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5),
23 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5,
32 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6),
33 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6,
42 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7),
43 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7,
51 DESCRIPTOR_TERMINATE_LIST,
52 PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3),
53 PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8,
61 static const PCIe_DDI_DESCRIPTOR
DdiList[] = {
65 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11),
66 PCIE_DDI_DATA_INITIALIZER(ConnectorTypeAutoDetect, Aux1, Hdp1)
70 DESCRIPTOR_TERMINATE_LIST,
71 PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15),
72 PCIE_DDI_DATA_INITIALIZER(ConnectorTypeAutoDetect, Aux2, Hdp2)
77 .Flags = DESCRIPTOR_TERMINATE_LIST,
85 InitEarly->GnbConfig.PcieComplexList = &
PcieComplex;
86 InitEarly->GnbConfig.PsppPolicy = 0;
101 HW_RXEN_SEED (ANY_SOCKET, ANY_CHANNEL, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B),
102 NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2),
103 NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1),
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
static const PCIe_COMPLEX_DESCRIPTOR PcieComplex
static const PCIe_DDI_DESCRIPTOR DdiList[]
static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[]
static const PCIe_PORT_DESCRIPTOR PortList[]