coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
chip.h File Reference
#include <intelblocks/cfg.h>
#include <soc/acpi.h>
#include <soc/gpio.h>
#include <soc/irq.h>
#include <stdint.h>
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Go to the source code of this file.

Data Structures

struct  pch_pcie_port
 UPD_PCH_PCIE_PORT: ForceEnable - Enable/Disable PCH PCIe port PortLinkSpeed - Port Link Speed. More...
 
struct  soc_intel_xeon_sp_cpx_config
 

Macros

#define MAX_PCH_PCIE_PORT   20
 

Typedefs

typedef struct soc_intel_xeon_sp_cpx_config config_t
 

Enumerations

enum  pcie_link_speed { PcieAuto = 0 , PcieGen1 , PcieGen2 , PcieGen3 }
 PCIe Link Speed Selection. More...
 
enum  ddr_freq_limit {
  DDR_AUTO = 0x0 , DDR_1333 = 0x5 , DDR_1600 = 0x7 , DDR_1866 = 0x9 ,
  DDR_2133 = 0xb , DDR_2400 = 0xd , DDR_2666 = 0xf , DDR_2933 = 0x11 ,
  DDR_3200 = 0x13
}
 enum for DDR Frequency Limit More...
 

Macro Definition Documentation

◆ MAX_PCH_PCIE_PORT

#define MAX_PCH_PCIE_PORT   20

Definition at line 12 of file chip.h.

Typedef Documentation

◆ config_t

Definition at line 1 of file chip.h.

Enumeration Type Documentation

◆ ddr_freq_limit

enum for DDR Frequency Limit

Enumerator
DDR_AUTO 
DDR_1333 
DDR_1600 
DDR_1866 
DDR_2133 
DDR_2400 
DDR_2666 
DDR_2933 
DDR_3200 

Definition at line 37 of file chip.h.

◆ pcie_link_speed

PCIe Link Speed Selection.

Enumerator
PcieAuto 
PcieGen1 
PcieGen2 
PcieGen3 

Definition at line 27 of file chip.h.