coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
sb_cimx.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef _CIMX_H_
4 #define _CIMX_H_
5 
6 /**
7  * AMD South Bridge CIMx entry point wrapper
8  */
9 void sb_Poweron_Init(void);
10 void sb_Before_Pci_Init(void);
11 void sb_After_Pci_Init(void);
12 void sb_Mid_Post_Init(void);
13 void sb_Late_Post(void);
14 void sb_Before_Pci_Restore_Init(void);
15 void sb_After_Pci_Restore_Init(void);
16 
17 /**
18  * CIMX not set the clock to 48Mhz until sbBeforePciInit,
19  * coreboot may need to set this even more earlier
20  */
21 void sb800_clk_output_48Mhz(void);
22 
23 #endif
sb_After_Pci_Init
void sb_After_Pci_Init(void)
Definition: late.c:259
sb_Mid_Post_Init
void sb_Mid_Post_Init(void)
Definition: late.c:266
sb_Before_Pci_Init
void sb_Before_Pci_Init(void)
South Bridge CIMx ramstage entry point wrapper.
Definition: late.c:252
sb_Before_Pci_Restore_Init
void sb_Before_Pci_Restore_Init(void)
Definition: late.c:280
sb_After_Pci_Restore_Init
void sb_After_Pci_Restore_Init(void)
Definition: late.c:287
sb800_clk_output_48Mhz
void sb800_clk_output_48Mhz(void)
CIMX not set the clock to 48Mhz until sbBeforePciInit, coreboot may need to set this even more earlie...
Definition: early.c:29
sb_Poweron_Init
void sb_Poweron_Init(void)
AMD South Bridge CIMx entry point wrapper.
Definition: early.c:12
sb_Late_Post
void sb_Late_Post(void)
Definition: late.c:273