46 case CB_SBGPP_RESET_ASSERT:
49 case CB_SBGPP_RESET_DEASSERT:
52 case IMC_FIRMWARE_FAIL:
65 #define HOST_IRQ_STAT 0x08
66 #define HOST_PORTS_IMPL 0x0c
68 #define HOST_CTL_AHCI_EN (1 << 31)
90 caps = (caps & 0x1F) + 1;
92 printk(
BIOS_DEBUG,
"Number of Ports: 0x%x, Port implemented(bit map): 0x%x\n", caps, ports);
142 #if CONFIG(HAVE_ACPI_TABLES)
151 static const struct pci_driver lpc_driver
__pci_driver = {
165 static const struct pci_driver ahci_driver
__pci_driver = {
171 static const struct pci_driver raid_driver
__pci_driver = {
176 static const struct pci_driver raid5_driver
__pci_driver = {
192 static const struct pci_driver usb_ohci123_driver
__pci_driver = {
198 static const struct pci_driver usb_ehci123_driver
__pci_driver = {
204 static const struct pci_driver usb_ohci4_driver
__pci_driver = {
217 static const struct pci_driver azalia_driver
__pci_driver = {
230 static const struct pci_driver gec_driver
__pci_driver = {
255 sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT;
262 sb_config->StdHeader.Func = SB_AFTER_PCI_INIT;
269 sb_config->StdHeader.Func = SB_MID_POST_INIT;
276 sb_config->StdHeader.Func = SB_LATE_POST_INIT;
283 sb_config->StdHeader.Func = SB_BEFORE_PCI_RESTORE_INIT;
290 sb_config->StdHeader.Func = SB_AFTER_PCI_RESTORE_INIT;
324 sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED;
326 sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0;
328 sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1;
330 sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED;
354 #if CONFIG(SB800_IMC_FAN_CONTROL)
356 #elif CONFIG(SB800_MANUAL_FAN_CONTROL)
unsigned long acpi_write_hpet(const struct device *device, unsigned long current, acpi_rsdp_t *rsdp)
static uint8_t pm_read8(uint8_t reg)
static void pm_write8(uint8_t reg, uint8_t value)
#define abcfg_reg(reg, mask, val)
static int acpi_is_wakeup_s3(void)
static void write32(void *addr, uint32_t val)
static uint32_t read32(const void *addr)
void setup_ioapic(void *ioapic_base, u8 ioapic_id)
void sb800_cimx_config(AMDSBCFG *sb_config)
South Bridge CIMx configuration.
enum fch_io_device device
#define printk(level,...)
void init_sb800_IMC_fans(struct device *dev)
void init_sb800_MANUAL_fans(struct device *dev)
static __always_inline u16 pci_read_config16(const struct device *dev, u16 reg)
static __always_inline u32 pci_read_config32(const struct device *dev, u16 reg)
static __always_inline u8 pci_read_config8(const struct device *dev, u16 reg)
static __always_inline void pci_write_config8(const struct device *dev, u16 reg, u8 val)
static const char * lpc_acpi_name(const struct device *dev)
static void sb800_init(void *chip_info)
Fill build time defaults.
BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL)
void sb_After_Pci_Init(void)
static AMDSBCFG sb_late_cfg
void sb_Mid_Post_Init(void)
static AMDSBCFG * sb_config
static struct device_operations usb_ops
static u32 sb800_callout_entry(u32 func, u32 data, void *config)
Entry point of Southbridge CIMx callout.
static struct device_operations sata_ops
static struct device_operations lpc_ops
static void sb800_enable(struct device *dev)
SB Cimx entry point sbBeforePciInit wrapper.
static const struct pci_driver lpc_driver __pci_driver
struct chip_operations southbridge_amd_cimx_sb800_ops
static void lpc_init(struct device *dev)
void sb_Before_Pci_Init(void)
South Bridge CIMx ramstage entry point wrapper.
void sb_Before_Pci_Restore_Init(void)
void sb_After_Pci_Restore_Init(void)
static struct device_operations gec_ops
static void ahci_raid_init(struct device *dev)
static struct device_operations azalia_ops
static void set_pci_irqs(void *unused)
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
#define BIOS_WARNING
BIOS_WARNING - Bad configuration.
void cmos_check_update_date(void)
void cmos_init(bool invalid)
#define PCI_DEVFN(slot, func)
#define PCI_INTERRUPT_LINE
#define PCI_COMMAND_MASTER
#define PCI_BASE_ADDRESS_5
void pci_dev_enable_resources(struct device *dev)
void pci_dev_read_resources(struct device *dev)
struct pci_operations pci_dev_ops_pci
Default device operation for PCI devices.
void pci_dev_set_resources(struct device *dev)
#define pci_ehci_read_resources
#define PCI_DID_ATI_SB800_LPC
#define PCI_DID_ATI_SB800_HDA
#define PCI_DID_ATI_SB800_SATA_RAID
#define PCI_DID_ATI_SB800_USB_18_2
#define PCI_DID_ATI_SB800_GEC
#define PCI_DID_ATI_SB800_USB_20_5
#define PCI_CLASS_STORAGE_RAID
#define PCI_DID_ATI_SB800_USB_18_0
#define PCI_CLASS_STORAGE_SATA
#define PCI_DID_ATI_SB800_SATA_AHCI
#define PCI_DID_ATI_SB800_SATA_RAID5
void scan_static_bus(struct device *bus)
void write_pci_cfg_irqs(void)
void write_pci_int_table(void)
static void lpc_read_resources(struct device *dev)
static void lpc_set_resources(struct device *dev)
void(* read_resources)(struct device *dev)
enum device_path_type type
DEVTREE_CONST struct device * sibling
DEVTREE_CONST void * chip_info