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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Go to the source code of this file.
Macros | |
#define | PEG_CAP 0xa2 |
#define | PEG_DCAP 0xa4 |
#define | PEG_LCAP 0xac |
#define | PEG_DSTS 0xaa |
#define | PEG_SLOTCAP 0xb4 |
#define | PEG_DCAP2 0xc4 /* 32bit */ |
#define | PEG_LCTL2 0xd0 |
#define | PEG_VC0RCTL 0x114 |
#define | PEG_ESD 0x144 /* 32bit */ |
#define | PEG_LE1D 0x150 /* 32bit */ |
#define | PEG_LE1A 0x158 /* 64bit */ |
#define | PEG_UESTS 0x1c4 |
#define | PEG_UESEV 0x1cc |
#define | PEG_CESTS 0x1d0 |
#define | PEG_L0SLAT 0x22c |
#define | PEG_AFE_PM_TMR 0xc28 |
#define PEG_AFE_PM_TMR 0xc28 |
Definition at line 32 of file pcie_graphics.h.
#define PEG_CAP 0xa2 |
Definition at line 7 of file pcie_graphics.h.
#define PEG_CESTS 0x1d0 |
Definition at line 28 of file pcie_graphics.h.
#define PEG_DCAP 0xa4 |
Definition at line 8 of file pcie_graphics.h.
#define PEG_DCAP2 0xc4 /* 32bit */ |
Definition at line 16 of file pcie_graphics.h.
#define PEG_DSTS 0xaa |
Definition at line 12 of file pcie_graphics.h.
#define PEG_ESD 0x144 /* 32bit */ |
Definition at line 22 of file pcie_graphics.h.
#define PEG_L0SLAT 0x22c |
Definition at line 30 of file pcie_graphics.h.
#define PEG_LCAP 0xac |
Definition at line 10 of file pcie_graphics.h.
#define PEG_LCTL2 0xd0 |
Definition at line 18 of file pcie_graphics.h.
#define PEG_LE1A 0x158 /* 64bit */ |
Definition at line 24 of file pcie_graphics.h.
#define PEG_LE1D 0x150 /* 32bit */ |
Definition at line 23 of file pcie_graphics.h.
#define PEG_SLOTCAP 0xb4 |
Definition at line 14 of file pcie_graphics.h.
#define PEG_UESEV 0x1cc |
Definition at line 27 of file pcie_graphics.h.
#define PEG_UESTS 0x1c4 |
Definition at line 26 of file pcie_graphics.h.
#define PEG_VC0RCTL 0x114 |
Definition at line 20 of file pcie_graphics.h.