coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
transition.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <arch/cache.h>
4 #include <arch/lib_helpers.h>
5 #include <arch/mmu.h>
6 #include <arch/transition.h>
7 #include <assert.h>
8 
10 {
11  /* Default weak implementation does nothing. */
12 }
13 
15 {
16  struct elx_state *elx = &exc_state->elx;
17  struct regs *regs = &exc_state->regs;
18  uint8_t elx_mode;
19 
20  elx->spsr = raw_read_spsr_el3();
21  elx_mode = get_mode_from_spsr(elx->spsr);
22 
23  if (elx_mode == SPSR_USE_H)
24  regs->sp = (uint64_t)&exc_state[1];
25  else
26  regs->sp = raw_read_sp_el0();
27 
28  elx->elr = raw_read_elr_el3();
29 
31 }
32 
33 void transition_to_el2(void *entry, void *arg, uint64_t spsr)
34 {
35  struct exc_state exc_state;
36  struct elx_state *elx = &exc_state.elx;
37  struct regs *regs = &exc_state.regs;
38 
39  regs->x[X0_INDEX] = (uint64_t)arg;
40  elx->elr = (uint64_t)entry;
41  elx->spsr = spsr;
42 
43  /*
44  * Policies enforced:
45  * 1. We support only transitions to EL2
46  * 2. We support transitions to Aarch64 mode only
47  *
48  * If any of the above conditions holds false, then we need a proper way
49  * to update SCR/HCR before removing the checks below
50  */
51  assert(get_el_from_spsr(spsr) == EL2 && !(spsr & SPSR_ERET_32));
52 
53  /* Initialize SCR with defaults for running without secure monitor
54  (disable all traps, enable all instructions, run NS at AArch64). */
55  raw_write_scr_el3(SCR_FIEN | SCR_API | SCR_APK | SCR_ST | SCR_RW |
57 
58  /* Initialize CPTR to not trap anything to EL3. */
59  raw_write_cptr_el3(CPTR_EL3_TCPAC_DISABLE | CPTR_EL3_TTA_DISABLE |
61 
62  /* ELR/SPSR: Write entry point and processor state of program */
63  raw_write_elr_el3(elx->elr);
64  raw_write_spsr_el3(elx->spsr);
65 
66  /* SCTLR: Initialize EL with everything disabled */
67  raw_write_sctlr_el2(SCTLR_RES1);
68 
69  /* SP_ELx: Initialize stack pointer */
70  raw_write_sp_el2(elx->sp_elx);
71 
72  /* Payloads expect to be entered with MMU disabled. Includes an ISB. */
73  mmu_disable();
74 
75  /* Eret to the entry point */
77 }
void mmu_disable(void)
#define assert(statement)
Definition: assert.h:74
struct bootblock_arg arg
Definition: decompressor.c:22
#define SCR_FIEN
Definition: lib_helpers.h:48
#define SCR_API
Definition: lib_helpers.h:44
#define SCR_ST
Definition: lib_helpers.h:38
#define SCR_RES1
Definition: lib_helpers.h:49
#define SCR_SMD
Definition: lib_helpers.h:34
#define SCR_NS
Definition: lib_helpers.h:30
#define SPSR_USE_H
Definition: lib_helpers.h:19
#define EL2
Definition: lib_helpers.h:12
#define SPSR_ERET_32
Definition: lib_helpers.h:22
#define SCR_RW
Definition: lib_helpers.h:37
#define CPTR_EL3_TCPAC_DISABLE
Definition: lib_helpers.h:74
#define SCTLR_RES1
Definition: lib_helpers.h:68
#define CPTR_EL3_TFP_DISABLE
Definition: lib_helpers.h:78
#define SCR_HCE
Definition: lib_helpers.h:35
#define CPTR_EL3_TTA_DISABLE
Definition: lib_helpers.h:76
#define SCR_APK
Definition: lib_helpers.h:43
const struct smm_save_state_ops *legacy_ops __weak
Definition: save_state.c:8
unsigned long long uint64_t
Definition: stdint.h:17
unsigned char uint8_t
Definition: stdint.h:8
uint64_t spsr
Definition: transition.h:98
uint64_t sp_elx
Definition: transition.h:100
uint64_t elr
Definition: transition.h:101
struct regs regs
Definition: transition.h:106
struct elx_state elx
Definition: transition.h:105
uint64_t x[31]
Definition: transition.h:94
uint64_t sp
Definition: transition.h:93
void __weak exc_dispatch(struct exc_state *exc_state, uint64_t id)
Definition: transition.c:9
void transition_to_el2(void *entry, void *arg, uint64_t spsr)
Definition: transition.c:33
void exc_entry(struct exc_state *exc_state, uint64_t id)
Definition: transition.c:14
void trans_switch(struct regs *regs)
static uint8_t get_mode_from_spsr(uint64_t spsr)
Definition: transition.h:139
static uint8_t get_el_from_spsr(uint64_t spsr)
Definition: transition.h:134