3 #ifndef SOUTHBRIDGE_INTEL_I82801JX_I82801JX_H
4 #define SOUTHBRIDGE_INTEL_I82801JX_I82801JX_H
6 #define DEFAULT_TBAR ((u8 *)0xfed1b000)
10 #define DEFAULT_PMBASE 0x00000500
11 #define DEFAULT_TCOBASE (DEFAULT_PMBASE + 0x60)
12 #define DEFAULT_GPIOBASE 0x00000580
16 #define GP_IO_USE_SEL 0x00
17 #define GP_IO_SEL 0x04
19 #define GPO_BLINK 0x18
21 #define GP_IO_USE_SEL2 0x30
22 #define GP_IO_SEL2 0x34
25 #define DEBUG_PERIODIC_SMIS 0
27 #define MAINBOARD_POWER_OFF 0
28 #define MAINBOARD_POWER_ON 1
29 #define MAINBOARD_POWER_KEEP 2
32 #define D31F0_ACPI_CNTL 0x44
33 #define ACPI_CNTL D31F0_ACPI_CNTL
34 #define D31F0_GPIO_BASE 0x48
35 #define D31F0_GPIO_CNTL 0x4c
36 #define D31F0_PIRQA_ROUT 0x60
37 #define D31F0_PIRQB_ROUT 0x61
38 #define D31F0_PIRQC_ROUT 0x62
39 #define D31F0_PIRQD_ROUT 0x63
40 #define D31F0_SERIRQ_CNTL 0x64
41 #define D31F0_PIRQE_ROUT 0x68
42 #define D31F0_PIRQF_ROUT 0x69
43 #define D31F0_PIRQG_ROUT 0x6a
44 #define D31F0_PIRQH_ROUT 0x6b
45 #define D31F0_LPC_IODEC 0x80
46 #define D31F0_LPC_EN 0x82
47 #define CNF2_LPC_EN (1 << 13)
48 #define CNF1_LPC_EN (1 << 12)
49 #define MC_LPC_EN (1 << 11)
50 #define KBC_LPC_EN (1 << 10)
51 #define GAMEH_LPC_EN (1 << 9)
52 #define GAMEL_LPC_EN (1 << 8)
53 #define FDD_LPC_EN (1 << 3)
54 #define LPT_LPC_EN (1 << 2)
55 #define COMB_LPC_EN (1 << 1)
56 #define COMA_LPC_EN (1 << 0)
57 #define D31F0_GEN1_DEC 0x84
58 #define D31F0_GEN2_DEC 0x88
59 #define D31F0_GEN3_DEC 0x8c
60 #define D31F0_GEN4_DEC 0x90
61 #define D31F0_C5_EXIT_TIMING 0xa8
62 #define D31F0_CxSTATE_CNF 0xa9
63 #define D31F0_C4TIMING_CNT 0xaa
64 #define D31F0_GPIO_ROUT 0xb8
67 #define D31F2_IDE_TIM_PRI 0x40
68 #define D31F2_IDE_TIM_SEC 0x42
69 #define D31F2_SIDX 0xa0
70 #define D31F2_SDAT 0xa4
73 #define D30F0_SMLT 0x1b
76 #define D28Fx_XCAP 0x42
77 #define D28Fx_SLCAP 0x54
84 #define I2C_EN (1 << 2)
85 #define SMB_SMI_EN (1 << 1)
86 #define HST_EN (1 << 0)
88 #define RCBA_V0CTL 0x0014
89 #define RCBA_V1CAP 0x001c
90 #define RCBA_V1CTL 0x0020
91 #define RCBA_V1STS 0x0026
92 #define RCBA_PAT 0x0030
93 #define RCBA_CIR1 0x0088
94 #define RCBA_ESD 0x0104
95 #define RCBA_ULD 0x0110
96 #define RCBA_ULBA 0x0118
97 #define RCBA_LCAP 0x01a4
98 #define RCBA_LCTL 0x01a8
99 #define RCBA_LSTS 0x01aa
100 #define RCBA_CIR2 0x01f4
101 #define RCBA_CIR3 0x01fc
102 #define RCBA_BCR 0x0220
103 #define RCBA_DMIC 0x0234
104 #define RCBA_RPFN 0x0238
105 #define RCBA_CIR13 0x0f20
106 #define RCBA_CIR5 0x1d40
107 #define RCBA_DMC 0x2010
108 #define RCBA_CIR6 0x2024
109 #define RCBA_CIR7 0x2034
110 #define RCBA_HPTC 0x3404
112 #define RCBA_BUC 0x3414
113 #define RCBA_FD 0x3418
114 #define RCBA_CG 0x341c
115 #define RCBA_FDSW 0x3420
116 #define RCBA_CIR8 0x3430
117 #define RCBA_CIR9 0x350c
118 #define RCBA_CIR10 0x352c
119 #define RCBA_MAP 0x35f0
138 #define BUC_LAND (1 << 5)
139 #define FD_SAD2 (1 << 25)
140 #define FD_TTD (1 << 24)
141 #define FD_PE6D (1 << 21)
142 #define FD_PE5D (1 << 20)
143 #define FD_PE4D (1 << 19)
144 #define FD_PE3D (1 << 18)
145 #define FD_PE2D (1 << 17)
146 #define FD_PE1D (1 << 16)
147 #define FD_EHCI1D (1 << 15)
148 #define FD_LBD (1 << 14)
149 #define FD_EHCI2D (1 << 13)
150 #define FD_U5D (1 << 12)
151 #define FD_U4D (1 << 11)
152 #define FD_U3D (1 << 10)
153 #define FD_U2D (1 << 9)
154 #define FD_U1D (1 << 8)
155 #define FD_U6D (1 << 7)
156 #define FD_HDAD (1 << 4)
157 #define FD_SD (1 << 3)
158 #define FD_SAD1 (1 << 2)
void i82801jx_setup_bars(void)
void i82801jx_lpc_setup(void)
void i82801jx_early_init(void)