#include <southbridge/intel/common/rcba.h>
#include <device/pci_ops.h>

Include dependency graph for i82801jx.h:

This graph shows which files directly or indirectly include this file:

Macros
#define	DEFAULT_TBAR ((u8 *)0xfed1b000)

#define	DEFAULT_PMBASE 0x00000500

#define	DEFAULT_TCOBASE (DEFAULT_PMBASE + 0x60)

#define	DEFAULT_GPIOBASE 0x00000580

#define	APM_CNT 0xb2

#define	GP_IO_USE_SEL 0x00

#define	GP_IO_SEL 0x04

#define	GP_LVL 0x0c

#define	GPO_BLINK 0x18

#define	GPI_INV 0x2c

#define	GP_IO_USE_SEL2 0x30

#define	GP_IO_SEL2 0x34

#define	GP_LVL2 0x38

#define	DEBUG_PERIODIC_SMIS 0

#define	MAINBOARD_POWER_OFF 0

#define	MAINBOARD_POWER_ON 1

#define	MAINBOARD_POWER_KEEP 2

#define	D31F0_ACPI_CNTL 0x44

#define	ACPI_CNTL D31F0_ACPI_CNTL

#define	D31F0_GPIO_BASE 0x48

#define	D31F0_GPIO_CNTL 0x4c

#define	D31F0_PIRQA_ROUT 0x60

#define	D31F0_PIRQB_ROUT 0x61

#define	D31F0_PIRQC_ROUT 0x62

#define	D31F0_PIRQD_ROUT 0x63

#define	D31F0_SERIRQ_CNTL 0x64

#define	D31F0_PIRQE_ROUT 0x68

#define	D31F0_PIRQF_ROUT 0x69

#define	D31F0_PIRQG_ROUT 0x6a

#define	D31F0_PIRQH_ROUT 0x6b

#define	D31F0_LPC_IODEC 0x80

#define	D31F0_LPC_EN 0x82

#define	CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */

#define	CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */

#define	MC_LPC_EN (1 << 11) /* 0x62/0x66 */

#define	KBC_LPC_EN (1 << 10) /* 0x60/0x64 */

#define	GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */

#define	GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */

#define	FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */

#define	LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */

#define	COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */

#define	COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */

#define	D31F0_GEN1_DEC 0x84

#define	D31F0_GEN2_DEC 0x88

#define	D31F0_GEN3_DEC 0x8c

#define	D31F0_GEN4_DEC 0x90

#define	D31F0_C5_EXIT_TIMING 0xa8

#define	D31F0_CxSTATE_CNF 0xa9

#define	D31F0_C4TIMING_CNT 0xaa

#define	D31F0_GPIO_ROUT 0xb8

#define	D31F2_IDE_TIM_PRI 0x40

#define	D31F2_IDE_TIM_SEC 0x42

#define	D31F2_SIDX 0xa0

#define	D31F2_SDAT 0xa4

#define	D30F0_SMLT 0x1b

#define	D28Fx_XCAP 0x42

#define	D28Fx_SLCAP 0x54

#define	SMB_BASE 0x20

#define	HOSTC 0x40

#define	I2C_EN (1 << 2)

#define	SMB_SMI_EN (1 << 1)

#define	HST_EN (1 << 0)

#define	RCBA_V0CTL 0x0014

#define	RCBA_V1CAP 0x001c

#define	RCBA_V1CTL 0x0020

#define	RCBA_V1STS 0x0026

#define	RCBA_PAT 0x0030

#define	RCBA_CIR1 0x0088

#define	RCBA_ESD 0x0104

#define	RCBA_ULD 0x0110

#define	RCBA_ULBA 0x0118

#define	RCBA_LCAP 0x01a4

#define	RCBA_LCTL 0x01a8

#define	RCBA_LSTS 0x01aa

#define	RCBA_CIR2 0x01f4

#define	RCBA_CIR3 0x01fc

#define	RCBA_BCR 0x0220

#define	RCBA_DMIC 0x0234

#define	RCBA_RPFN 0x0238

#define	RCBA_CIR13 0x0f20

#define	RCBA_CIR5 0x1d40

#define	RCBA_DMC 0x2010

#define	RCBA_CIR6 0x2024

#define	RCBA_CIR7 0x2034

#define	RCBA_HPTC 0x3404

#define	GCS 0x3410

#define	RCBA_BUC 0x3414

#define	RCBA_FD 0x3418 /* Function Disable, see below. */

#define	RCBA_CG 0x341c

#define	RCBA_FDSW 0x3420

#define	RCBA_CIR8 0x3430

#define	RCBA_CIR9 0x350c

#define	RCBA_CIR10 0x352c

#define	RCBA_MAP 0x35f0 /* UHCI controller #6 remapping */

#define	D31IP 0x3100 /* 32bit */

#define	D30IP 0x3104 /* 32bit R0: does not generate interrupt */

#define	D29IP 0x3108 /* 32bit */

#define	D28IP 0x310c /* 32bit */

#define	D27IP 0x3110 /* 32bit */

#define	D26IP 0x3114 /* 32bit */

#define	D25IP 0x3114 /* 32bit */

#define	D31IR 0x3140 /* 16bit */

#define	D30IR 0x3142 /* 16bit R0: does not generate interrupt */

#define	D29IR 0x3144 /* 16bit */

#define	D28IR 0x3146 /* 16bit */

#define	D27IR 0x3148 /* 16bit */

#define	D26IR 0x314c /* 16bit */

#define	D25IR 0x3150 /* 16bit */

#define	OIC 0x31ff /* 8bit */

#define	BUC_LAND (1 << 5) /* LAN */

#define	FD_SAD2 (1 << 25) /* SATA #2 */

#define	FD_TTD (1 << 24) /* Thermal Throttle */

#define	FD_PE6D (1 << 21) /* PCIe root port 6 */

#define	FD_PE5D (1 << 20) /* PCIe root port 5 */

#define	FD_PE4D (1 << 19) /* PCIe root port 4 */

#define	FD_PE3D (1 << 18) /* PCIe root port 3 */

#define	FD_PE2D (1 << 17) /* PCIe root port 2 */

#define	FD_PE1D (1 << 16) /* PCIe root port 1 */

#define	FD_EHCI1D (1 << 15) /* EHCI #1 */

#define	FD_LBD (1 << 14) /* LPC bridge */

#define	FD_EHCI2D (1 << 13) /* EHCI #2 */

#define	FD_U5D (1 << 12) /* UHCI #5 */

#define	FD_U4D (1 << 11) /* UHCI #4 */

#define	FD_U3D (1 << 10) /* UHCI #3 */

#define	FD_U2D (1 << 9) /* UHCI #2 */

#define	FD_U1D (1 << 8) /* UHCI #1 */

#define	FD_U6D (1 << 7) /* UHCI #6 */

#define	FD_HDAD (1 << 4) /* HD audio */

#define	FD_SD (1 << 3) /* SMBus */

#define	FD_SAD1 (1 << 2) /* SATA #1 */

Functions
void	i82801jx_lpc_setup (void)

void	i82801jx_setup_bars (void)

void	i82801jx_early_init (void)

Macro Definition Documentation

◆ ACPI_CNTL

#define ACPI_CNTL D31F0_ACPI_CNTL

Definition at line 33 of file i82801jx.h.

◆ APM_CNT

#define APM_CNT 0xb2

Definition at line 14 of file i82801jx.h.

◆ BUC_LAND

#define BUC_LAND (1 << 5) /* LAN */

Definition at line 138 of file i82801jx.h.

◆ CNF1_LPC_EN

#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */

Definition at line 48 of file i82801jx.h.

◆ CNF2_LPC_EN

#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */

Definition at line 47 of file i82801jx.h.

◆ COMA_LPC_EN

#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */

Definition at line 56 of file i82801jx.h.

◆ COMB_LPC_EN

#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */

Definition at line 55 of file i82801jx.h.

◆ D25IP

#define D25IP 0x3114 /* 32bit */

Definition at line 127 of file i82801jx.h.

◆ D25IR

#define D25IR 0x3150 /* 16bit */

Definition at line 135 of file i82801jx.h.

◆ D26IP

#define D26IP 0x3114 /* 32bit */

Definition at line 126 of file i82801jx.h.

◆ D26IR

#define D26IR 0x314c /* 16bit */

Definition at line 134 of file i82801jx.h.

◆ D27IP

#define D27IP 0x3110 /* 32bit */

Definition at line 125 of file i82801jx.h.

◆ D27IR

#define D27IR 0x3148 /* 16bit */

Definition at line 133 of file i82801jx.h.

◆ D28Fx_SLCAP

#define D28Fx_SLCAP 0x54

Definition at line 77 of file i82801jx.h.

◆ D28Fx_XCAP

#define D28Fx_XCAP 0x42

Definition at line 76 of file i82801jx.h.

◆ D28IP

#define D28IP 0x310c /* 32bit */

Definition at line 124 of file i82801jx.h.

◆ D28IR

#define D28IR 0x3146 /* 16bit */

Definition at line 132 of file i82801jx.h.

◆ D29IP

#define D29IP 0x3108 /* 32bit */

Definition at line 123 of file i82801jx.h.

◆ D29IR

#define D29IR 0x3144 /* 16bit */

Definition at line 131 of file i82801jx.h.

◆ D30F0_SMLT

#define D30F0_SMLT 0x1b

Definition at line 73 of file i82801jx.h.

◆ D30IP

#define D30IP 0x3104 /* 32bit R0: does not generate interrupt */

Definition at line 122 of file i82801jx.h.

◆ D30IR

#define D30IR 0x3142 /* 16bit R0: does not generate interrupt */

Definition at line 130 of file i82801jx.h.

◆ D31F0_ACPI_CNTL

#define D31F0_ACPI_CNTL 0x44

Definition at line 32 of file i82801jx.h.

◆ D31F0_C4TIMING_CNT

#define D31F0_C4TIMING_CNT 0xaa

Definition at line 63 of file i82801jx.h.

◆ D31F0_C5_EXIT_TIMING

#define D31F0_C5_EXIT_TIMING 0xa8

Definition at line 61 of file i82801jx.h.

◆ D31F0_CxSTATE_CNF

#define D31F0_CxSTATE_CNF 0xa9

Definition at line 62 of file i82801jx.h.

◆ D31F0_GEN1_DEC

#define D31F0_GEN1_DEC 0x84

Definition at line 57 of file i82801jx.h.

◆ D31F0_GEN2_DEC

#define D31F0_GEN2_DEC 0x88

Definition at line 58 of file i82801jx.h.

◆ D31F0_GEN3_DEC

#define D31F0_GEN3_DEC 0x8c

Definition at line 59 of file i82801jx.h.

◆ D31F0_GEN4_DEC

#define D31F0_GEN4_DEC 0x90

Definition at line 60 of file i82801jx.h.

◆ D31F0_GPIO_BASE

#define D31F0_GPIO_BASE 0x48

Definition at line 34 of file i82801jx.h.

◆ D31F0_GPIO_CNTL

#define D31F0_GPIO_CNTL 0x4c

Definition at line 35 of file i82801jx.h.

◆ D31F0_GPIO_ROUT

#define D31F0_GPIO_ROUT 0xb8

Definition at line 64 of file i82801jx.h.

◆ D31F0_LPC_EN

#define D31F0_LPC_EN 0x82

Definition at line 46 of file i82801jx.h.

◆ D31F0_LPC_IODEC

#define D31F0_LPC_IODEC 0x80

Definition at line 45 of file i82801jx.h.

◆ D31F0_PIRQA_ROUT

#define D31F0_PIRQA_ROUT 0x60

Definition at line 36 of file i82801jx.h.

◆ D31F0_PIRQB_ROUT

#define D31F0_PIRQB_ROUT 0x61

Definition at line 37 of file i82801jx.h.

◆ D31F0_PIRQC_ROUT

#define D31F0_PIRQC_ROUT 0x62

Definition at line 38 of file i82801jx.h.

◆ D31F0_PIRQD_ROUT

#define D31F0_PIRQD_ROUT 0x63

Definition at line 39 of file i82801jx.h.

◆ D31F0_PIRQE_ROUT

#define D31F0_PIRQE_ROUT 0x68

Definition at line 41 of file i82801jx.h.

◆ D31F0_PIRQF_ROUT

#define D31F0_PIRQF_ROUT 0x69

Definition at line 42 of file i82801jx.h.

◆ D31F0_PIRQG_ROUT

#define D31F0_PIRQG_ROUT 0x6a

Definition at line 43 of file i82801jx.h.

◆ D31F0_PIRQH_ROUT

#define D31F0_PIRQH_ROUT 0x6b

Definition at line 44 of file i82801jx.h.

◆ D31F0_SERIRQ_CNTL

#define D31F0_SERIRQ_CNTL 0x64

Definition at line 40 of file i82801jx.h.

◆ D31F2_IDE_TIM_PRI

#define D31F2_IDE_TIM_PRI 0x40

Definition at line 67 of file i82801jx.h.

◆ D31F2_IDE_TIM_SEC

#define D31F2_IDE_TIM_SEC 0x42

Definition at line 68 of file i82801jx.h.

◆ D31F2_SDAT

#define D31F2_SDAT 0xa4

Definition at line 70 of file i82801jx.h.

◆ D31F2_SIDX

#define D31F2_SIDX 0xa0

Definition at line 69 of file i82801jx.h.

◆ D31IP

#define D31IP 0x3100 /* 32bit */

Definition at line 121 of file i82801jx.h.

◆ D31IR

#define D31IR 0x3140 /* 16bit */

Definition at line 129 of file i82801jx.h.

◆ DEBUG_PERIODIC_SMIS

#define DEBUG_PERIODIC_SMIS 0

Definition at line 25 of file i82801jx.h.

◆ DEFAULT_GPIOBASE

#define DEFAULT_GPIOBASE 0x00000580

Definition at line 12 of file i82801jx.h.

◆ DEFAULT_PMBASE

#define DEFAULT_PMBASE 0x00000500

Definition at line 10 of file i82801jx.h.

◆ DEFAULT_TBAR

#define DEFAULT_TBAR ((u8 *)0xfed1b000)

Definition at line 6 of file i82801jx.h.

◆ DEFAULT_TCOBASE

#define DEFAULT_TCOBASE (DEFAULT_PMBASE + 0x60)

Definition at line 11 of file i82801jx.h.

◆ FD_EHCI1D

#define FD_EHCI1D (1 << 15) /* EHCI #1 */

Definition at line 147 of file i82801jx.h.

◆ FD_EHCI2D

#define FD_EHCI2D (1 << 13) /* EHCI #2 */

Definition at line 149 of file i82801jx.h.

◆ FD_HDAD

#define FD_HDAD (1 << 4) /* HD audio */

Definition at line 156 of file i82801jx.h.

◆ FD_LBD

#define FD_LBD (1 << 14) /* LPC bridge */

Definition at line 148 of file i82801jx.h.

◆ FD_PE1D

#define FD_PE1D (1 << 16) /* PCIe root port 1 */

Definition at line 146 of file i82801jx.h.

◆ FD_PE2D

#define FD_PE2D (1 << 17) /* PCIe root port 2 */

Definition at line 145 of file i82801jx.h.

◆ FD_PE3D

#define FD_PE3D (1 << 18) /* PCIe root port 3 */

Definition at line 144 of file i82801jx.h.

◆ FD_PE4D

#define FD_PE4D (1 << 19) /* PCIe root port 4 */

Definition at line 143 of file i82801jx.h.

◆ FD_PE5D

#define FD_PE5D (1 << 20) /* PCIe root port 5 */

Definition at line 142 of file i82801jx.h.

◆ FD_PE6D

#define FD_PE6D (1 << 21) /* PCIe root port 6 */

Definition at line 141 of file i82801jx.h.

◆ FD_SAD1

#define FD_SAD1 (1 << 2) /* SATA #1 */

Definition at line 158 of file i82801jx.h.

◆ FD_SAD2

#define FD_SAD2 (1 << 25) /* SATA #2 */

Definition at line 139 of file i82801jx.h.

◆ FD_SD

#define FD_SD (1 << 3) /* SMBus */

Definition at line 157 of file i82801jx.h.

◆ FD_TTD

#define FD_TTD (1 << 24) /* Thermal Throttle */

Definition at line 140 of file i82801jx.h.

◆ FD_U1D

#define FD_U1D (1 << 8) /* UHCI #1 */

Definition at line 154 of file i82801jx.h.

◆ FD_U2D

#define FD_U2D (1 << 9) /* UHCI #2 */

Definition at line 153 of file i82801jx.h.

◆ FD_U3D

#define FD_U3D (1 << 10) /* UHCI #3 */

Definition at line 152 of file i82801jx.h.

◆ FD_U4D

#define FD_U4D (1 << 11) /* UHCI #4 */

Definition at line 151 of file i82801jx.h.

◆ FD_U5D

#define FD_U5D (1 << 12) /* UHCI #5 */

Definition at line 150 of file i82801jx.h.

◆ FD_U6D

#define FD_U6D (1 << 7) /* UHCI #6 */

Definition at line 155 of file i82801jx.h.

◆ FDD_LPC_EN

#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */

Definition at line 53 of file i82801jx.h.

◆ GAMEH_LPC_EN

#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */

Definition at line 51 of file i82801jx.h.

◆ GAMEL_LPC_EN

#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */

Definition at line 52 of file i82801jx.h.

◆ GCS

#define GCS 0x3410

Definition at line 111 of file i82801jx.h.

◆ GP_IO_SEL

#define GP_IO_SEL 0x04

Definition at line 17 of file i82801jx.h.

◆ GP_IO_SEL2

#define GP_IO_SEL2 0x34

Definition at line 22 of file i82801jx.h.

◆ GP_IO_USE_SEL

#define GP_IO_USE_SEL 0x00

Definition at line 16 of file i82801jx.h.

◆ GP_IO_USE_SEL2

#define GP_IO_USE_SEL2 0x30

Definition at line 21 of file i82801jx.h.

◆ GP_LVL

#define GP_LVL 0x0c

Definition at line 18 of file i82801jx.h.

◆ GP_LVL2

#define GP_LVL2 0x38

Definition at line 23 of file i82801jx.h.

◆ GPI_INV

#define GPI_INV 0x2c

Definition at line 20 of file i82801jx.h.

◆ GPO_BLINK

#define GPO_BLINK 0x18

Definition at line 19 of file i82801jx.h.

◆ HOSTC

#define HOSTC 0x40

Definition at line 81 of file i82801jx.h.

◆ HST_EN

#define HST_EN (1 << 0)

Definition at line 86 of file i82801jx.h.

◆ I2C_EN

#define I2C_EN (1 << 2)

Definition at line 84 of file i82801jx.h.

◆ KBC_LPC_EN

#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */

Definition at line 50 of file i82801jx.h.

◆ LPT_LPC_EN

#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */

Definition at line 54 of file i82801jx.h.

◆ MAINBOARD_POWER_KEEP

#define MAINBOARD_POWER_KEEP 2

Definition at line 29 of file i82801jx.h.

◆ MAINBOARD_POWER_OFF

#define MAINBOARD_POWER_OFF 0

Definition at line 27 of file i82801jx.h.

◆ MAINBOARD_POWER_ON

#define MAINBOARD_POWER_ON 1

Definition at line 28 of file i82801jx.h.

◆ MC_LPC_EN

#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */

Definition at line 49 of file i82801jx.h.

◆ OIC

#define OIC 0x31ff /* 8bit */

Definition at line 136 of file i82801jx.h.

◆ RCBA_BCR

#define RCBA_BCR 0x0220

Definition at line 102 of file i82801jx.h.

◆ RCBA_BUC

#define RCBA_BUC 0x3414

Definition at line 112 of file i82801jx.h.

◆ RCBA_CG

#define RCBA_CG 0x341c

Definition at line 114 of file i82801jx.h.

◆ RCBA_CIR1

#define RCBA_CIR1 0x0088

Definition at line 93 of file i82801jx.h.

◆ RCBA_CIR10

#define RCBA_CIR10 0x352c

Definition at line 118 of file i82801jx.h.

◆ RCBA_CIR13

#define RCBA_CIR13 0x0f20

Definition at line 105 of file i82801jx.h.

◆ RCBA_CIR2

#define RCBA_CIR2 0x01f4

Definition at line 100 of file i82801jx.h.

◆ RCBA_CIR3

#define RCBA_CIR3 0x01fc

Definition at line 101 of file i82801jx.h.

◆ RCBA_CIR5

#define RCBA_CIR5 0x1d40

Definition at line 106 of file i82801jx.h.

◆ RCBA_CIR6

#define RCBA_CIR6 0x2024

Definition at line 108 of file i82801jx.h.

◆ RCBA_CIR7

#define RCBA_CIR7 0x2034

Definition at line 109 of file i82801jx.h.

◆ RCBA_CIR8

#define RCBA_CIR8 0x3430

Definition at line 116 of file i82801jx.h.

◆ RCBA_CIR9

#define RCBA_CIR9 0x350c

Definition at line 117 of file i82801jx.h.

◆ RCBA_DMC

#define RCBA_DMC 0x2010

Definition at line 107 of file i82801jx.h.

◆ RCBA_DMIC

#define RCBA_DMIC 0x0234

Definition at line 103 of file i82801jx.h.

◆ RCBA_ESD

#define RCBA_ESD 0x0104

Definition at line 94 of file i82801jx.h.

◆ RCBA_FD

#define RCBA_FD 0x3418 /* Function Disable, see below. */

Definition at line 113 of file i82801jx.h.

◆ RCBA_FDSW

#define RCBA_FDSW 0x3420

Definition at line 115 of file i82801jx.h.

◆ RCBA_HPTC

#define RCBA_HPTC 0x3404

Definition at line 110 of file i82801jx.h.

◆ RCBA_LCAP

#define RCBA_LCAP 0x01a4

Definition at line 97 of file i82801jx.h.

◆ RCBA_LCTL

#define RCBA_LCTL 0x01a8

Definition at line 98 of file i82801jx.h.

◆ RCBA_LSTS

#define RCBA_LSTS 0x01aa

Definition at line 99 of file i82801jx.h.

◆ RCBA_MAP

#define RCBA_MAP 0x35f0 /* UHCI controller #6 remapping */

Definition at line 119 of file i82801jx.h.

◆ RCBA_PAT

#define RCBA_PAT 0x0030

Definition at line 92 of file i82801jx.h.

◆ RCBA_RPFN

#define RCBA_RPFN 0x0238

Definition at line 104 of file i82801jx.h.

◆ RCBA_ULBA

#define RCBA_ULBA 0x0118

Definition at line 96 of file i82801jx.h.

◆ RCBA_ULD

#define RCBA_ULD 0x0110

Definition at line 95 of file i82801jx.h.

◆ RCBA_V0CTL

#define RCBA_V0CTL 0x0014

Definition at line 88 of file i82801jx.h.

◆ RCBA_V1CAP

#define RCBA_V1CAP 0x001c

Definition at line 89 of file i82801jx.h.

◆ RCBA_V1CTL

#define RCBA_V1CTL 0x0020

Definition at line 90 of file i82801jx.h.

◆ RCBA_V1STS

#define RCBA_V1STS 0x0026

Definition at line 91 of file i82801jx.h.

◆ SMB_BASE

#define SMB_BASE 0x20

Definition at line 80 of file i82801jx.h.

◆ SMB_SMI_EN

#define SMB_SMI_EN (1 << 1)

Definition at line 85 of file i82801jx.h.

Function Documentation

◆ i82801jx_early_init()

void i82801jx_early_init ( void )

Definition at line 68 of file early_init.c.

References BIOS_DEBUG, enable_smbus(), ENV_ROMSTAGE, GCS, i82801jx_setup_bars(), mainboard_gpio_map, OIC, PCI_DEV, pci_read_config8(), pci_write_config8(), printk, RCBA32, RCBA8, setup_pch_gpios(), TCO_BASE, and write_pmbase16().

Referenced by mainboard_romstage_entry().

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◆ i82801jx_lpc_setup()

void i82801jx_lpc_setup ( void )

Definition at line 12 of file early_init.c.

References device::chip_info, CNF1_LPC_EN, CNF2_LPC_EN, COMA_LPC_EN, COMB_LPC_EN, config, D31F0_GEN1_DEC, D31F0_GEN2_DEC, D31F0_GEN3_DEC, D31F0_GEN4_DEC, D31F0_LPC_EN, D31F0_LPC_IODEC, D31F0_SERIRQ_CNTL, FDD_LPC_EN, GAMEH_LPC_EN, GAMEL_LPC_EN, KBC_LPC_EN, LPT_LPC_EN, MC_LPC_EN, PCI_DEV, pci_write_config16(), pci_write_config32(), pci_write_config8(), and pcidev_on_root().

Referenced by bootblock_early_southbridge_init().

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◆ i82801jx_setup_bars()

void i82801jx_setup_bars ( void )

Definition at line 48 of file early_init.c.

References D31F0_ACPI_CNTL, D31F0_GPIO_BASE, D31F0_GPIO_CNTL, D31F0_PMBASE, DEFAULT_GPIOBASE, DEFAULT_PMBASE, PCI_DEV, pci_or_config8(), pci_write_config32(), pci_write_config8(), and RCBA.

Referenced by bootblock_early_southbridge_init(), and i82801jx_early_init().

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Macros

Functions

Macro Definition Documentation

◆ ACPI_CNTL

◆ APM_CNT

◆ BUC_LAND

◆ CNF1_LPC_EN

◆ CNF2_LPC_EN

◆ COMA_LPC_EN

◆ COMB_LPC_EN

◆ D25IP

◆ D25IR

◆ D26IP

◆ D26IR

◆ D27IP

◆ D27IR

◆ D28Fx_SLCAP

◆ D28Fx_XCAP

◆ D28IP

◆ D28IR

◆ D29IP

◆ D29IR

◆ D30F0_SMLT

◆ D30IP

◆ D30IR

◆ D31F0_ACPI_CNTL

◆ D31F0_C4TIMING_CNT

◆ D31F0_C5_EXIT_TIMING

◆ D31F0_CxSTATE_CNF

◆ D31F0_GEN1_DEC

◆ D31F0_GEN2_DEC

◆ D31F0_GEN3_DEC

◆ D31F0_GEN4_DEC

◆ D31F0_GPIO_BASE

◆ D31F0_GPIO_CNTL

◆ D31F0_GPIO_ROUT

◆ D31F0_LPC_EN

◆ D31F0_LPC_IODEC

◆ D31F0_PIRQA_ROUT

◆ D31F0_PIRQB_ROUT

◆ D31F0_PIRQC_ROUT

◆ D31F0_PIRQD_ROUT

◆ D31F0_PIRQE_ROUT

◆ D31F0_PIRQF_ROUT

◆ D31F0_PIRQG_ROUT

◆ D31F0_PIRQH_ROUT

◆ D31F0_SERIRQ_CNTL

◆ D31F2_IDE_TIM_PRI

◆ D31F2_IDE_TIM_SEC

◆ D31F2_SDAT

◆ D31F2_SIDX

◆ D31IP

◆ D31IR

◆ DEBUG_PERIODIC_SMIS

◆ DEFAULT_GPIOBASE

◆ DEFAULT_PMBASE

◆ DEFAULT_TBAR

◆ DEFAULT_TCOBASE

◆ FD_EHCI1D

◆ FD_EHCI2D

◆ FD_HDAD

◆ FD_LBD

◆ FD_PE1D

◆ FD_PE2D

◆ FD_PE3D

◆ FD_PE4D

◆ FD_PE5D

◆ FD_PE6D

◆ FD_SAD1

◆ FD_SAD2

◆ FD_SD

◆ FD_TTD

◆ FD_U1D

◆ FD_U2D

◆ FD_U3D

◆ FD_U4D

◆ FD_U5D

◆ FD_U6D

◆ FDD_LPC_EN

◆ GAMEH_LPC_EN