coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
psp_verstage.h
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #ifndef PSP_VERSTAGE_H
4 #define PSP_VERSTAGE_H
5 
6 #include <2crypto.h>
7 #include <amdblocks/psp_efs.h>
8 #include <bl_uapp/bl_syscall_public.h>
9 #include <stdint.h>
10 #include <soc/psp_transfer.h>
11 
12 #define EMBEDDED_FW_SIGNATURE 0x55aa55aa
13 #define PSP_COOKIE 0x50535024 /* 'PSP$' */
14 #define BHD_COOKIE 0x44484224 /* 'DHB$ */
15 
16 #define PSP_VBOOT_ERROR_SUBCODE 0x0D5D0000
17 
18 #define POSTCODE_ENTERED_PSP_VERSTAGE 0x00
19 #define POSTCODE_CONSOLE_INIT 0x01
20 #define POSTCODE_EARLY_INIT 0x02
21 #define POSTCODE_LATE_INIT 0x03
22 #define POSTCODE_VERSTAGE_MAIN 0x04
23 #define POSTCODE_VERSTAGE_S0I3_RESUME 0x05
24 
25 #define POSTCODE_SAVE_BUFFERS 0x0E
26 #define POSTCODE_UPDATE_BOOT_REGION 0x0F
27 
28 #define POSTCODE_DEFAULT_BUFFER_SIZE_NOTICE 0xC0
29 #define POSTCODE_WORKBUF_RESIZE_WARNING 0xC1
30 #define POSTCODE_WORKBUF_SAVE_ERROR 0xC2
31 #define POSTCODE_WORKBUF_BUFFER_SIZE_ERROR 0xC3
32 #define POSTCODE_ROMSIG_MISMATCH_ERROR 0xC4
33 #define POSTCODE_PSP_COOKIE_MISMATCH_ERROR 0xC5
34 #define POSTCODE_BHD_COOKIE_MISMATCH_ERROR 0xC6
35 #define POSTCODE_UPDATE_PSP_BIOS_DIR_ERROR 0xC7
36 #define POSTCODE_FMAP_REGION_MISSING 0xC8
37 #define POSTCODE_AMD_FW_MISSING 0xC9
38 #define POSTCODE_CMOS_RECOVERY 0xCA
39 #define POSTCODE_EARLY_INIT_ERROR 0xCB
40 #define POSTCODE_INIT_TPM_FAILED 0xCC
41 
42 
43 #define POSTCODE_UNMAP_SPI_ROM 0xF0
44 #define POSTCODE_UNMAP_FCH_DEVICES 0xF1
45 #define POSTCODE_LEAVING_VERSTAGE 0xF2
46 
47 #define SPI_ADDR_MASK 0x00ffffff
48 #define MIN_TRANSFER_BUFFER_SIZE (8 * KiB)
49 #define MIN_WORKBUF_TRANSFER_SIZE (MIN_TRANSFER_BUFFER_SIZE - TRANSFER_INFO_SIZE)
50 
51 void test_svc_calls(void);
56 void verstage_soc_aoac_init(void);
57 void verstage_soc_espi_init(void);
58 void verstage_soc_i2c_init(void);
59 void verstage_soc_spi_init(void);
60 uintptr_t *map_spi_rom(void);
61 
62 uint32_t update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset);
65 int platform_set_sha_op(enum vb2_hash_algorithm hash_alg,
66  struct sha_generic_data *sha_op);
67 void platform_report_mode(int developer_mode_enabled);
68 
69 #endif /* PSP_VERSTAGE_H */
uint64_t address
Definition: fw_cfg_if.h:0
void verstage_soc_spi_init(void)
Definition: fch.c:175
void platform_report_mode(int developer_mode_enabled)
Definition: chipset.c:37
void verstage_soc_aoac_init(void)
Definition: fch.c:169
uint32_t verstage_soc_early_init(void)
Definition: fch.c:150
void verstage_mainboard_tpm_init(void)
Definition: verstage.c:44
void test_svc_calls(void)
void verstage_soc_espi_init(void)
Definition: fch.c:155
void verstage_mainboard_espi_init(void)
Definition: verstage.c:21
uintptr_t * map_spi_rom(void)
Definition: fch.c:91
int platform_set_sha_op(enum vb2_hash_algorithm hash_alg, struct sha_generic_data *sha_op)
Definition: chipset.c:22
uint32_t update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset)
Definition: chipset.c:7
uint32_t unmap_fch_devices(void)
Definition: fch.c:126
void verstage_soc_i2c_init(void)
Definition: fch.c:163
uint32_t save_uapp_data(void *address, uint32_t size)
Definition: chipset.c:12
uint32_t get_bios_dir_addr(struct embedded_firmware *ef_table)
Definition: chipset.c:17
unsigned int uint32_t
Definition: stdint.h:14
unsigned long uintptr_t
Definition: stdint.h:21
static struct sha_generic_data sha_op
Definition: vboot_crypto.c:14