coreboot
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dsi.h
Go to the documentation of this file.
1
/* SPDX-License-Identifier: GPL-2.0-only */
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3
#ifndef _DSI_REG_H_
4
#define _DSI_REG_H_
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#include <
soc/dsi_common.h
>
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#include <types.h>
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/* DSI features */
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#define MTK_DSI_MIPI_RATIO_NUMERATOR 102
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#define MTK_DSI_MIPI_RATIO_DENOMINATOR 100
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#define MTK_DSI_DATA_RATE_MIN_MHZ 50
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#define MTK_DSI_HAVE_SIZE_CON 0
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#define PIXEL_STREAM_CUSTOM_HEADER 0
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/* MIPITX is SOC specific and cannot live in common. */
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/* MIPITX_REG */
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struct
mipi_tx_regs
{
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u32
dsi_con
;
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u32
dsi_clock_lane
;
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u32
dsi_data_lane
[4];
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u8
reserved0
[40];
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u32
dsi_top_con
;
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u32
dsi_bg_con
;
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u8
reserved1
[8];
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u32
dsi_pll_con0
;
28
u32
dsi_pll_con1
;
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u32
dsi_pll_con2
;
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u32
dsi_pll_con3
;
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u32
dsi_pll_chg
;
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u32
dsi_pll_top
;
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u32
dsi_pll_pwr
;
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u8
reserved2
[4];
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u32
dsi_rgs
;
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u32
dsi_gpi_en
;
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u32
dsi_gpi_pull
;
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u32
dsi_phy_sel
;
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u32
dsi_sw_ctrl_en
;
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u32
dsi_sw_ctrl_con0
;
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u32
dsi_sw_ctrl_con1
;
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u32
dsi_sw_ctrl_con2
;
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u32
dsi_dbg_con
;
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u32
dsi_dbg_out
;
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u32
dsi_apb_async_sta
;
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};
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check_member
(
mipi_tx_regs
, dsi_top_con, 0x40);
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check_member
(
mipi_tx_regs
, dsi_pll_pwr, 0x68);
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static
struct
mipi_tx_regs
*
const
mipi_tx0
= (
void
*)
MIPI_TX0_BASE
;
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static
struct
mipi_tx_regs
*
const
mipi_tx1
= (
void
*)
MIPI_TX0_BASE
;
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/* MIPITX_DSI0_CON */
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enum
{
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RG_DSI0_LDOCORE_EN
=
BIT
(0),
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RG_DSI0_CKG_LDOOUT_EN
=
BIT
(1),
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RG_DSI0_BCLK_SEL
= (3 << 2),
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RG_DSI0_LD_IDX_SEL
= (7 << 4),
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RG_DSI0_PHYCLK_SEL
= (2 << 8),
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RG_DSI0_DSICLK_FREQ_SEL
=
BIT
(10),
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RG_DSI0_LPTX_CLMP_EN
=
BIT
(11)
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};
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/* MIPITX_DSI0_CLOCK_LANE */
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enum
{
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LDOOUT_EN
=
BIT
(0),
68
CKLANE_EN
=
BIT
(1),
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IPLUS1
=
BIT
(2),
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LPTX_IPLUS2
=
BIT
(3),
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LPTX_IMINUS
=
BIT
(4),
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LPCD_IPLUS
=
BIT
(5),
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LPCD_IMLUS
=
BIT
(6),
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RT_CODE
= (0xf << 8)
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};
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/* MIPITX_DSI_TOP_CON */
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enum
{
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RG_DSI_LNT_INTR_EN
=
BIT
(0),
80
RG_DSI_LNT_HS_BIAS_EN
=
BIT
(1),
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RG_DSI_LNT_IMP_CAL_EN
=
BIT
(2),
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RG_DSI_LNT_TESTMODE_EN
=
BIT
(3),
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RG_DSI_LNT_IMP_CAL_CODE
= (0xf << 4),
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RG_DSI_LNT_AIO_SEL
= (7 << 8),
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RG_DSI_PAD_TIE_LOW_EN
=
BIT
(11),
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RG_DSI_DEBUG_INPUT_EN
=
BIT
(12),
87
RG_DSI_PRESERVE
= (7 << 13)
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};
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/* MIPITX_DSI_BG_CON */
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enum
{
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RG_DSI_BG_CORE_EN
=
BIT
(0),
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RG_DSI_BG_CKEN
=
BIT
(1),
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RG_DSI_BG_DIV
= (0x3 << 2),
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RG_DSI_BG_FAST_CHARGE
=
BIT
(4),
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RG_DSI_V12_SEL
= (7 << 5),
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RG_DSI_V10_SEL
= (7 << 8),
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RG_DSI_V072_SEL
= (7 << 11),
99
RG_DSI_V04_SEL
= (7 << 14),
100
RG_DSI_V032_SEL
= (7 << 17),
101
RG_DSI_V02_SEL
= (7 << 20),
102
rsv_23
=
BIT
(23),
103
RG_DSI_BG_R1_TRIM
= (0xf << 24),
104
RG_DSI_BG_R2_TRIM
= (0xf << 28)
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};
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/* MIPITX_DSI_PLL_CON0 */
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enum
{
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RG_DSI0_MPPLL_PLL_EN
=
BIT
(0),
110
RG_DSI0_MPPLL_PREDIV
= (3 << 1),
111
RG_DSI0_MPPLL_TXDIV0
= (3 << 3),
112
RG_DSI0_MPPLL_TXDIV1
= (3 << 5),
113
RG_DSI0_MPPLL_POSDIV
= (7 << 7),
114
RG_DSI0_MPPLL_MONVC_EN
=
BIT
(10),
115
RG_DSI0_MPPLL_MONREF_EN
=
BIT
(11),
116
RG_DSI0_MPPLL_VOD_EN
=
BIT
(12)
117
};
118
119
/* MIPITX_DSI_PLL_CON1 */
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enum
{
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RG_DSI0_MPPLL_SDM_FRA_EN
=
BIT
(0),
122
RG_DSI0_MPPLL_SDM_SSC_PH_INIT
=
BIT
(1),
123
RG_DSI0_MPPLL_SDM_SSC_EN
=
BIT
(2),
124
RG_DSI0_MPPLL_SDM_SSC_PRD
= (0xffff << 16)
125
};
126
127
/* MIPITX_DSI_PLL_PWR */
128
enum
{
129
RG_DSI_MPPLL_SDM_PWR_ON
=
BIT
(0),
130
RG_DSI_MPPLL_SDM_ISO_EN
=
BIT
(1),
131
RG_DSI_MPPLL_SDM_PWR_ACK
=
BIT
(8)
132
};
133
134
/* LVDS_TX1_REG */
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struct
lvds_tx1_regs
{
136
u32
lvdstx1_ctl1
;
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u32
lvdstx1_ctl2
;
138
u32
lvdstx1_ctl3
;
139
u32
lvdstx1_ctl4
;
140
u32
lvdstx1_ctl5
;
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u32
vopll_ctl1
;
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u32
vopll_ctl2
;
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u32
vopll_ctl3
;
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};
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static
struct
lvds_tx1_regs
*
const
lvds_tx1
= (
void
*)(
MIPI_TX0_BASE
+ 0x800);
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static
struct
lvds_tx1_regs
*
const
lvds_tx2
= (
void
*)(
MIPI_TX1_BASE
+ 0x800);
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/* LVDS_VOPLL_CTRL3 */
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enum
{
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RG_LVDSTX_21EDG
=
BIT
(0),
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RG_LVDSTX_21LEV
=
BIT
(1),
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RG_LVDSTX_51EDG
=
BIT
(2),
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RG_LVDSTX_51LEV
=
BIT
(3),
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RG_AD_LVDSTX_PWR_ACK
=
BIT
(4),
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RG_DA_LVDS_ISO_EN
=
BIT
(8),
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RG_DA_LVDSTX_PWR_ON
=
BIT
(9)
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};
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160
/* SOC specific functions */
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void
mtk_dsi_pin_drv_ctrl
(
void
);
162
163
#endif
dsi_common.h
BIT
#define BIT(nr)
Definition:
ec_commands.h:45
MIPI_TX0_BASE
@ MIPI_TX0_BASE
Definition:
addressmap.h:33
MIPI_TX1_BASE
@ MIPI_TX1_BASE
Definition:
addressmap.h:34
RG_DSI0_MPPLL_PREDIV
@ RG_DSI0_MPPLL_PREDIV
Definition:
dsi.h:110
RG_DSI0_MPPLL_TXDIV0
@ RG_DSI0_MPPLL_TXDIV0
Definition:
dsi.h:111
RG_DSI0_MPPLL_VOD_EN
@ RG_DSI0_MPPLL_VOD_EN
Definition:
dsi.h:116
RG_DSI0_MPPLL_PLL_EN
@ RG_DSI0_MPPLL_PLL_EN
Definition:
dsi.h:109
RG_DSI0_MPPLL_MONVC_EN
@ RG_DSI0_MPPLL_MONVC_EN
Definition:
dsi.h:114
RG_DSI0_MPPLL_MONREF_EN
@ RG_DSI0_MPPLL_MONREF_EN
Definition:
dsi.h:115
RG_DSI0_MPPLL_POSDIV
@ RG_DSI0_MPPLL_POSDIV
Definition:
dsi.h:113
RG_DSI0_MPPLL_TXDIV1
@ RG_DSI0_MPPLL_TXDIV1
Definition:
dsi.h:112
RG_DSI0_MPPLL_SDM_SSC_PH_INIT
@ RG_DSI0_MPPLL_SDM_SSC_PH_INIT
Definition:
dsi.h:122
RG_DSI0_MPPLL_SDM_SSC_EN
@ RG_DSI0_MPPLL_SDM_SSC_EN
Definition:
dsi.h:123
RG_DSI0_MPPLL_SDM_SSC_PRD
@ RG_DSI0_MPPLL_SDM_SSC_PRD
Definition:
dsi.h:124
RG_DSI0_MPPLL_SDM_FRA_EN
@ RG_DSI0_MPPLL_SDM_FRA_EN
Definition:
dsi.h:121
rsv_23
@ rsv_23
Definition:
dsi.h:102
RG_DSI_BG_CKEN
@ RG_DSI_BG_CKEN
Definition:
dsi.h:93
RG_DSI_BG_R1_TRIM
@ RG_DSI_BG_R1_TRIM
Definition:
dsi.h:103
RG_DSI_BG_CORE_EN
@ RG_DSI_BG_CORE_EN
Definition:
dsi.h:92
RG_DSI_V04_SEL
@ RG_DSI_V04_SEL
Definition:
dsi.h:99
RG_DSI_V10_SEL
@ RG_DSI_V10_SEL
Definition:
dsi.h:97
RG_DSI_V072_SEL
@ RG_DSI_V072_SEL
Definition:
dsi.h:98
RG_DSI_BG_R2_TRIM
@ RG_DSI_BG_R2_TRIM
Definition:
dsi.h:104
RG_DSI_V032_SEL
@ RG_DSI_V032_SEL
Definition:
dsi.h:100
RG_DSI_BG_DIV
@ RG_DSI_BG_DIV
Definition:
dsi.h:94
RG_DSI_V12_SEL
@ RG_DSI_V12_SEL
Definition:
dsi.h:96
RG_DSI_BG_FAST_CHARGE
@ RG_DSI_BG_FAST_CHARGE
Definition:
dsi.h:95
RG_DSI_V02_SEL
@ RG_DSI_V02_SEL
Definition:
dsi.h:101
RG_DSI_MPPLL_SDM_PWR_ACK
@ RG_DSI_MPPLL_SDM_PWR_ACK
Definition:
dsi.h:131
RG_DSI_MPPLL_SDM_PWR_ON
@ RG_DSI_MPPLL_SDM_PWR_ON
Definition:
dsi.h:129
RG_DSI_MPPLL_SDM_ISO_EN
@ RG_DSI_MPPLL_SDM_ISO_EN
Definition:
dsi.h:130
RG_DSI_LNT_INTR_EN
@ RG_DSI_LNT_INTR_EN
Definition:
dsi.h:79
RG_DSI_LNT_IMP_CAL_EN
@ RG_DSI_LNT_IMP_CAL_EN
Definition:
dsi.h:81
RG_DSI_LNT_HS_BIAS_EN
@ RG_DSI_LNT_HS_BIAS_EN
Definition:
dsi.h:80
RG_DSI_LNT_TESTMODE_EN
@ RG_DSI_LNT_TESTMODE_EN
Definition:
dsi.h:82
RG_DSI_PAD_TIE_LOW_EN
@ RG_DSI_PAD_TIE_LOW_EN
Definition:
dsi.h:85
RG_DSI_PRESERVE
@ RG_DSI_PRESERVE
Definition:
dsi.h:87
RG_DSI_LNT_AIO_SEL
@ RG_DSI_LNT_AIO_SEL
Definition:
dsi.h:84
RG_DSI_LNT_IMP_CAL_CODE
@ RG_DSI_LNT_IMP_CAL_CODE
Definition:
dsi.h:83
RG_DSI_DEBUG_INPUT_EN
@ RG_DSI_DEBUG_INPUT_EN
Definition:
dsi.h:86
mipi_tx1
static struct mipi_tx_regs *const mipi_tx1
Definition:
dsi.h:52
RG_LVDSTX_21LEV
@ RG_LVDSTX_21LEV
Definition:
dsi.h:152
RG_DA_LVDSTX_PWR_ON
@ RG_DA_LVDSTX_PWR_ON
Definition:
dsi.h:157
RG_DA_LVDS_ISO_EN
@ RG_DA_LVDS_ISO_EN
Definition:
dsi.h:156
RG_LVDSTX_21EDG
@ RG_LVDSTX_21EDG
Definition:
dsi.h:151
RG_AD_LVDSTX_PWR_ACK
@ RG_AD_LVDSTX_PWR_ACK
Definition:
dsi.h:155
RG_LVDSTX_51EDG
@ RG_LVDSTX_51EDG
Definition:
dsi.h:153
RG_LVDSTX_51LEV
@ RG_LVDSTX_51LEV
Definition:
dsi.h:154
mipi_tx0
static struct mipi_tx_regs *const mipi_tx0
Definition:
dsi.h:51
lvds_tx1
static struct lvds_tx1_regs *const lvds_tx1
Definition:
dsi.h:146
lvds_tx2
static struct lvds_tx1_regs *const lvds_tx2
Definition:
dsi.h:147
mtk_dsi_pin_drv_ctrl
void mtk_dsi_pin_drv_ctrl(void)
Definition:
dsi.c:116
check_member
check_member(mipi_tx_regs, dsi_top_con, 0x40)
LPCD_IMLUS
@ LPCD_IMLUS
Definition:
dsi.h:73
LPTX_IPLUS2
@ LPTX_IPLUS2
Definition:
dsi.h:70
LPCD_IPLUS
@ LPCD_IPLUS
Definition:
dsi.h:72
CKLANE_EN
@ CKLANE_EN
Definition:
dsi.h:68
IPLUS1
@ IPLUS1
Definition:
dsi.h:69
RT_CODE
@ RT_CODE
Definition:
dsi.h:74
LDOOUT_EN
@ LDOOUT_EN
Definition:
dsi.h:67
LPTX_IMINUS
@ LPTX_IMINUS
Definition:
dsi.h:71
RG_DSI0_BCLK_SEL
@ RG_DSI0_BCLK_SEL
Definition:
dsi.h:58
RG_DSI0_DSICLK_FREQ_SEL
@ RG_DSI0_DSICLK_FREQ_SEL
Definition:
dsi.h:61
RG_DSI0_LDOCORE_EN
@ RG_DSI0_LDOCORE_EN
Definition:
dsi.h:56
RG_DSI0_CKG_LDOOUT_EN
@ RG_DSI0_CKG_LDOOUT_EN
Definition:
dsi.h:57
RG_DSI0_LPTX_CLMP_EN
@ RG_DSI0_LPTX_CLMP_EN
Definition:
dsi.h:62
RG_DSI0_LD_IDX_SEL
@ RG_DSI0_LD_IDX_SEL
Definition:
dsi.h:59
RG_DSI0_PHYCLK_SEL
@ RG_DSI0_PHYCLK_SEL
Definition:
dsi.h:60
u32
uint32_t u32
Definition:
stdint.h:51
u8
uint8_t u8
Definition:
stdint.h:45
lvds_tx1_regs
Definition:
dsi.h:135
lvds_tx1_regs::vopll_ctl3
u32 vopll_ctl3
Definition:
dsi.h:143
lvds_tx1_regs::vopll_ctl2
u32 vopll_ctl2
Definition:
dsi.h:142
lvds_tx1_regs::lvdstx1_ctl2
u32 lvdstx1_ctl2
Definition:
dsi.h:137
lvds_tx1_regs::lvdstx1_ctl1
u32 lvdstx1_ctl1
Definition:
dsi.h:136
lvds_tx1_regs::lvdstx1_ctl4
u32 lvdstx1_ctl4
Definition:
dsi.h:139
lvds_tx1_regs::lvdstx1_ctl3
u32 lvdstx1_ctl3
Definition:
dsi.h:138
lvds_tx1_regs::lvdstx1_ctl5
u32 lvdstx1_ctl5
Definition:
dsi.h:140
lvds_tx1_regs::vopll_ctl1
u32 vopll_ctl1
Definition:
dsi.h:141
mipi_tx_regs
Definition:
dsi.h:19
mipi_tx_regs::dsi_data_lane
u32 dsi_data_lane[4]
Definition:
dsi.h:22
mipi_tx_regs::dsi_sw_ctrl_con2
u32 dsi_sw_ctrl_con2
Definition:
dsi.h:42
mipi_tx_regs::reserved0
u8 reserved0[40]
Definition:
dsi.h:23
mipi_tx_regs::dsi_gpi_en
u32 dsi_gpi_en
Definition:
dsi.h:36
mipi_tx_regs::dsi_pll_con2
u32 dsi_pll_con2
Definition:
dsi.h:29
mipi_tx_regs::dsi_bg_con
u32 dsi_bg_con
Definition:
dsi.h:25
mipi_tx_regs::dsi_pll_con3
u32 dsi_pll_con3
Definition:
dsi.h:30
mipi_tx_regs::dsi_gpi_pull
u32 dsi_gpi_pull
Definition:
dsi.h:37
mipi_tx_regs::dsi_pll_top
u32 dsi_pll_top
Definition:
dsi.h:32
mipi_tx_regs::dsi_rgs
u32 dsi_rgs
Definition:
dsi.h:35
mipi_tx_regs::dsi_dbg_con
u32 dsi_dbg_con
Definition:
dsi.h:43
mipi_tx_regs::dsi_pll_chg
u32 dsi_pll_chg
Definition:
dsi.h:31
mipi_tx_regs::dsi_pll_con0
u32 dsi_pll_con0
Definition:
dsi.h:27
mipi_tx_regs::reserved1
u8 reserved1[8]
Definition:
dsi.h:26
mipi_tx_regs::dsi_pll_con1
u32 dsi_pll_con1
Definition:
dsi.h:28
mipi_tx_regs::dsi_pll_pwr
u32 dsi_pll_pwr
Definition:
dsi.h:33
mipi_tx_regs::dsi_phy_sel
u32 dsi_phy_sel
Definition:
dsi.h:38
mipi_tx_regs::dsi_top_con
u32 dsi_top_con
Definition:
dsi.h:24
mipi_tx_regs::dsi_con
u32 dsi_con
Definition:
dsi.h:20
mipi_tx_regs::reserved2
u8 reserved2[4]
Definition:
dsi.h:34
mipi_tx_regs::dsi_clock_lane
u32 dsi_clock_lane
Definition:
dsi.h:21
mipi_tx_regs::dsi_sw_ctrl_con1
u32 dsi_sw_ctrl_con1
Definition:
dsi.h:41
mipi_tx_regs::dsi_dbg_out
u32 dsi_dbg_out
Definition:
dsi.h:44
mipi_tx_regs::dsi_sw_ctrl_en
u32 dsi_sw_ctrl_en
Definition:
dsi.h:39
mipi_tx_regs::dsi_sw_ctrl_con0
u32 dsi_sw_ctrl_con0
Definition:
dsi.h:40
mipi_tx_regs::dsi_apb_async_sta
u32 dsi_apb_async_sta
Definition:
dsi.h:45
src
soc
mediatek
mt8173
include
soc
dsi.h
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