coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
romstage.c File Reference
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Functions

unsigned int variant_get_spd_index (void)
 
bool variant_is_dual_channel (const unsigned int spd_index)
 

Variables

const struct usb2_port_config mainboard_usb2_ports [MAX_USB2_PORTS]
 
const struct usb3_port_config mainboard_usb3_ports [MAX_USB3_PORTS]
 

Function Documentation

◆ variant_get_spd_index()

unsigned int variant_get_spd_index ( void  )

Definition at line 8 of file romstage.c.

References get_gpios().

Referenced by mb_get_spd_map().

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◆ variant_is_dual_channel()

bool variant_is_dual_channel ( const unsigned int  spd_index)

Definition at line 14 of file romstage.c.

Referenced by mb_get_spd_map().

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Variable Documentation

◆ mainboard_usb2_ports

const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS]
Initial value:
= {
{ 0x0064, 1, 0,
{ 0x0052, 1, 0,
{ 0x0040, 1, USB_OC_PIN_SKIP,
{ 0x0040, 1, USB_OC_PIN_SKIP,
{ 0x0040, 1, USB_OC_PIN_SKIP,
{ 0x0040, 1, USB_OC_PIN_SKIP,
{ 0x0040, 1, USB_OC_PIN_SKIP,
{ 0x0123, 1, 3,
}
#define USB_OC_PIN_SKIP
Definition: pei_data.h:27
@ USB_PORT_BACK_PANEL
Definition: pei_data.h:30
@ USB_PORT_INTERNAL
Definition: pei_data.h:35

Definition at line 14 of file romstage.c.

◆ mainboard_usb3_ports

const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS]
Initial value:
= {
{ 1, 0 },
{ 1, 0 },
{ 0, USB_OC_PIN_SKIP },
{ 0, USB_OC_PIN_SKIP },
}

Definition at line 14 of file romstage.c.