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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <device/device.h>
#include <device/pci.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <cpu/intel/smm_reloc.h>
#include <southbridge/intel/common/pmbase.h>
#include <southbridge/intel/common/pmutil.h>
Go to the source code of this file.
Functions | |
u16 | get_pmbase (void) |
static int | smi_enabled (void) |
static void | smm_southbridge_enable (uint16_t pm1_events) |
void | global_smi_enable (void) |
Set the EOS bit and enable SMI generation from southbridge. More... | |
void | smm_southbridge_clear_state (void) |
Definition at line 13 of file smi.c.
References lpc_get_pmbase().
Referenced by smm_southbridge_clear_state().
Set the EOS bit and enable SMI generation from southbridge.
Definition at line 71 of file smi.c.
References dump_all_status(), GBL_EN, PWRBTN_EN, smi_enabled(), and smm_southbridge_enable().
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static |
Definition at line 18 of file smi.c.
References APMC_EN, BIOS_DEBUG, BIOS_INFO, BIOS_SPEW, CONFIG, lpc_get_pmbase(), pch_log_state(), printk, read_pmbase32(), and SMI_EN.
Referenced by global_smi_enable(), and smm_southbridge_clear_state().
Definition at line 80 of file smi.c.
References reset_gpe0_status(), reset_pm1_status(), reset_smi_status(), reset_tco_status(), and smi_enabled().
Definition at line 38 of file smi.c.
References APMC_EN, CONFIG, EOS, GBL_SMI_EN, GPE0_EN, PERIODIC_EN, PM1_EN, PME_B0_EN, read_pmbase32(), SLP_SMI_EN, SMI_EN, TCO_EN, write_pmbase16(), and write_pmbase32().
Referenced by global_smi_enable().