coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
pmutil.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <types.h>
4 #include <console/console.h>
5 #include <device/pci_def.h>
6 #include <southbridge/intel/common/pmbase.h>
7 #include <southbridge/intel/common/gpio.h>
8 
9 #include "pmutil.h"
10 
11 void alt_gpi_mask(u16 clr, u16 set)
12 {
13  u16 alt_gp = read_pmbase16(ALT_GP_SMI_EN);
14  alt_gp &= ~clr;
15  alt_gp |= set;
16  write_pmbase16(ALT_GP_SMI_EN, alt_gp);
17 }
18 
19 void gpe0_mask(u32 clr, u32 set)
20 {
21  u32 gpe0 = read_pmbase32(GPE0_EN);
22  gpe0 &= ~clr;
23  gpe0 |= set;
24  write_pmbase32(GPE0_EN, gpe0);
25 }
26 
27 /**
28  * @brief read and clear PM1_STS
29  * @return PM1_STS register
30  */
31 u16 reset_pm1_status(void)
32 {
33  u16 reg16 = read_pmbase16(PM1_STS);
34  /* set status bits are cleared by writing 1 to them */
35  write_pmbase16(PM1_STS, reg16);
36 
37  return reg16;
38 }
39 
40 void dump_pm1_status(u16 pm1_sts)
41 {
42  printk(BIOS_SPEW, "PM1_STS: ");
43  if (pm1_sts & (1 << 15)) printk(BIOS_SPEW, "WAK ");
44  if (pm1_sts & (1 << 14)) printk(BIOS_SPEW, "PCIEXPWAK ");
45  if (pm1_sts & (1 << 11)) printk(BIOS_SPEW, "PRBTNOR ");
46  if (pm1_sts & (1 << 10)) printk(BIOS_SPEW, "RTC ");
47  if (pm1_sts & (1 << 8)) printk(BIOS_SPEW, "PWRBTN ");
48  if (pm1_sts & (1 << 5)) printk(BIOS_SPEW, "GBL ");
49  if (pm1_sts & (1 << 4)) printk(BIOS_SPEW, "BM ");
50  if (pm1_sts & (1 << 0)) printk(BIOS_SPEW, "TMROF ");
51  printk(BIOS_SPEW, "\n");
52 
53  int reg16 = read_pmbase16(PM1_EN);
54  printk(BIOS_SPEW, "PM1_EN: %x\n", reg16);
55 }
56 
57 /**
58  * @brief read and clear SMI_STS
59  * @return SMI_STS register
60  */
61 u32 reset_smi_status(void)
62 {
63  u32 reg32;
64 
65  reg32 = read_pmbase32(SMI_STS);
66  /* set status bits are cleared by writing 1 to them */
67  write_pmbase32(SMI_STS, reg32);
68 
69  return reg32;
70 }
71 
72 void dump_smi_status(u32 smi_sts)
73 {
74  printk(BIOS_DEBUG, "SMI_STS: ");
75  if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
76  if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
77  if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
78  if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
79  if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
80  if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
81  if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
82  if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
83  if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
84  if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
85  if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
86  if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
87  if (smi_sts & (1 << 9)) printk(BIOS_DEBUG, "GPE0 ");
88  if (smi_sts & (1 << 8)) printk(BIOS_DEBUG, "PM1 ");
89  if (smi_sts & (1 << 6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
90  if (smi_sts & (1 << 5)) printk(BIOS_DEBUG, "APM ");
91  if (smi_sts & (1 << 4)) printk(BIOS_DEBUG, "SLP_SMI ");
92  if (smi_sts & (1 << 3)) printk(BIOS_DEBUG, "LEGACY_USB ");
93  if (smi_sts & (1 << 2)) printk(BIOS_DEBUG, "BIOS ");
94  printk(BIOS_DEBUG, "\n");
95 }
96 
97 /**
98  * @brief read and clear GPE0_STS
99  * @return GPE0_STS register
100  */
101 u64 reset_gpe0_status(void)
102 {
103  u32 reg_h, reg_l;
104 
105  reg_l = read_pmbase32(GPE0_STS);
106  reg_h = read_pmbase32(GPE0_STS + 4);
107  /* set status bits are cleared by writing 1 to them */
108  write_pmbase32(GPE0_STS, reg_l);
109  write_pmbase32(GPE0_STS + 4, reg_h);
110 
111  return (((u64)reg_h) << 32) | reg_l;
112 }
113 
114 void dump_gpe0_status(u64 gpe0_sts)
115 {
116  int i;
117  printk(BIOS_DEBUG, "GPE0_STS: ");
118  if (gpe0_sts & (1LL << 32)) printk(BIOS_DEBUG, "USB6 ");
119  for (i=31; i>= 16; i--) {
120  if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
121  }
122  if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
123  if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
124  if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
125  if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
126  if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
127  if (gpe0_sts & (1 << 9)) printk(BIOS_DEBUG, "PCI_EXP ");
128  if (gpe0_sts & (1 << 8)) printk(BIOS_DEBUG, "RI ");
129  if (gpe0_sts & (1 << 7)) printk(BIOS_DEBUG, "SMB_WAK ");
130  if (gpe0_sts & (1 << 6)) printk(BIOS_DEBUG, "TCO_SCI ");
131  if (gpe0_sts & (1 << 5)) printk(BIOS_DEBUG, "USB5 ");
132  if (gpe0_sts & (1 << 4)) printk(BIOS_DEBUG, "USB2 ");
133  if (gpe0_sts & (1 << 3)) printk(BIOS_DEBUG, "USB1 ");
134  if (gpe0_sts & (1 << 2)) printk(BIOS_DEBUG, "SWGPE ");
135  if (gpe0_sts & (1 << 1)) printk(BIOS_DEBUG, "HOT_PLUG ");
136  if (gpe0_sts & (1 << 0)) printk(BIOS_DEBUG, "THRM ");
137  printk(BIOS_DEBUG, "\n");
138 }
139 
140 /**
141  * @brief read and clear TCOx_STS
142  * @return TCOx_STS registers
143  */
144 u32 reset_tco_status(void)
145 {
146  u32 reg32;
147 
148  reg32 = read_pmbase32(TCO1_STS);
149  /*
150  * set status bits are cleared by writing 1 to them, but don't
151  * clear BOOT_STS before SECOND_TO_STS.
152  */
153  write_pmbase32(TCO1_STS, reg32 & ~BOOT_STS);
154  if (reg32 & BOOT_STS)
155  write_pmbase32(TCO1_STS, BOOT_STS);
156 
157  return reg32;
158 }
159 
160 void dump_tco_status(u32 tco_sts)
161 {
162  printk(BIOS_DEBUG, "TCO_STS: ");
163  if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
164  if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
165  if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
166  if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
167  if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
168  if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
169  if (tco_sts & (1 << 9)) printk(BIOS_DEBUG, "DMISCI ");
170  if (tco_sts & (1 << 8)) printk(BIOS_DEBUG, "BIOSWR ");
171  if (tco_sts & (1 << 7)) printk(BIOS_DEBUG, "NEWCENTURY ");
172  if (tco_sts & (1 << 3)) printk(BIOS_DEBUG, "TIMEOUT ");
173  if (tco_sts & (1 << 2)) printk(BIOS_DEBUG, "TCO_INT ");
174  if (tco_sts & (1 << 1)) printk(BIOS_DEBUG, "SW_TCO ");
175  if (tco_sts & (1 << 0)) printk(BIOS_DEBUG, "NMI2SMI ");
176  printk(BIOS_DEBUG, "\n");
177 }
178 
179 /**
180  * @brief Set the EOS bit
181  */
182 void smi_set_eos(void)
183 {
184  u8 reg8;
185 
186  reg8 = read_pmbase8(SMI_EN);
187  reg8 |= EOS;
188  write_pmbase8(SMI_EN, reg8);
189 }
190 
191 void dump_alt_gp_smi_status(u16 alt_gp_smi_sts)
192 {
193  int i;
194  printk(BIOS_DEBUG, "ALT_GP_SMI_STS: ");
195  for (i=15; i>= 0; i--) {
196  if (alt_gp_smi_sts & (1 << i)) printk(BIOS_DEBUG, "GPI%d ", i);
197  }
198  printk(BIOS_DEBUG, "\n");
199 }
200 
201 /**
202  * @brief read and clear ALT_GP_SMI_STS
203  * @return ALT_GP_SMI_STS register
204  */
205 u16 reset_alt_gp_smi_status(void)
206 {
207  u16 reg16;
208 
209  reg16 = read_pmbase16(ALT_GP_SMI_STS);
210  /* set status bits are cleared by writing 1 to them */
211  write_pmbase16(ALT_GP_SMI_STS, reg16);
212 
213  return reg16;
214 }
215 
216 void dump_all_status(void)
217 {
218  dump_smi_status(reset_smi_status());
219  dump_pm1_status(reset_pm1_status());
220  dump_gpe0_status(reset_gpe0_status());
221  dump_alt_gp_smi_status(reset_alt_gp_smi_status());
222  dump_tco_status(reset_tco_status());
223 }
PM1_EN
#define PM1_EN
Definition: pm.h:21
SMI_STS
#define SMI_STS
Definition: pm.h:50
GPE0_STS
#define GPE0_STS(x)
Definition: pm.h:81
PM1_STS
#define PM1_STS
Definition: pm.h:12
GPE0_EN
#define GPE0_EN(x)
Definition: pm.h:99
SMI_EN
#define SMI_EN
Definition: pm.h:32
EOS
#define EOS
Definition: pm.h:48
printk
#define printk(level,...)
Definition: stdlib.h:16
BIOS_DEBUG
#define BIOS_DEBUG
BIOS_DEBUG - Verbose output.
Definition: loglevel.h:128
BIOS_SPEW
#define BIOS_SPEW
BIOS_SPEW - Excessively verbose output.
Definition: loglevel.h:142
pci_def.h
write_pmbase16
void write_pmbase16(const u8 addr, const u16 val)
Definition: pmbase.c:43
read_pmbase32
u32 read_pmbase32(const u8 addr)
Definition: pmbase.c:57
write_pmbase32
void write_pmbase32(const u8 addr, const u32 val)
Definition: pmbase.c:36
read_pmbase16
u16 read_pmbase16(const u8 addr)
Definition: pmbase.c:64
write_pmbase8
void write_pmbase8(const u8 addr, const u8 val)
Definition: pmbase.c:50
read_pmbase8
u8 read_pmbase8(const u8 addr)
Definition: pmbase.c:71
BOOT_STS
#define BOOT_STS
Definition: pmutil.h:105
TCO1_STS
#define TCO1_STS
Definition: smbus.h:7
ALT_GP_SMI_STS
#define ALT_GP_SMI_STS
Definition: pch.h:462
ALT_GP_SMI_EN
#define ALT_GP_SMI_EN
Definition: pch.h:461
reset_smi_status
u32 reset_smi_status(void)
read and clear SMI_STS
Definition: pmutil.c:61
reset_gpe0_status
u64 reset_gpe0_status(void)
read and clear GPE0_STS
Definition: pmutil.c:101
alt_gpi_mask
void alt_gpi_mask(u16 clr, u16 set)
Definition: pmutil.c:11
reset_alt_gp_smi_status
u16 reset_alt_gp_smi_status(void)
read and clear ALT_GP_SMI_STS
Definition: pmutil.c:205
gpe0_mask
void gpe0_mask(u32 clr, u32 set)
Definition: pmutil.c:19
dump_alt_gp_smi_status
void dump_alt_gp_smi_status(u16 alt_gp_smi_sts)
Definition: pmutil.c:191
smi_set_eos
void smi_set_eos(void)
Set the EOS bit.
Definition: pmutil.c:182
dump_pm1_status
void dump_pm1_status(u16 pm1_sts)
Definition: pmutil.c:40
dump_all_status
void dump_all_status(void)
Definition: pmutil.c:216
reset_pm1_status
u16 reset_pm1_status(void)
read and clear PM1_STS
Definition: pmutil.c:31
reset_tco_status
u32 reset_tco_status(void)
read and clear TCOx_STS
Definition: pmutil.c:144
dump_gpe0_status
void dump_gpe0_status(u64 gpe0_sts)
Definition: pmutil.c:114
dump_tco_status
void dump_tco_status(u32 tco_sts)
Definition: pmutil.c:160
dump_smi_status
void dump_smi_status(u32 smi_sts)
Definition: pmutil.c:72
u64
uint64_t u64
Definition: stdint.h:54
u32
uint32_t u32
Definition: stdint.h:51
u16
uint16_t u16
Definition: stdint.h:48
u8
uint8_t u8
Definition: stdint.h:45