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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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#include <assert.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <device/pci_ops.h>
#include <mainboard/emulation/qemu-i440fx/memory.h>
#include <mainboard/emulation/qemu-i440fx/fw_cfg.h>
#include <cpu/intel/smm_reloc.h>
#include "q35.h"
Go to the source code of this file.
Macros | |
#define | __SIMPLE_DEVICE__ |
#define | EXT_TSEG_MBYTES 0x50 |
#define | SMRAMC 0x9d |
#define | C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) |
#define | G_SMRAME (1 << 3) |
#define | D_LCK (1 << 4) |
#define | D_CLS (1 << 5) |
#define | D_OPEN (1 << 6) |
#define | ESMRAMC 0x9e |
#define | T_EN (1 << 0) |
#define | TSEG_SZ_MASK (3 << 1) |
#define | H_SMRAME (1 << 7) |
Functions | |
static uint32_t | encode_pciexbar_length (void) |
uint32_t | make_pciexbar (void) |
void | mainboard_machine_check (void) |
void | smm_region (uintptr_t *start, size_t *size) |
void | smm_lock (void) |
Definition at line 15 of file memmap.c.
References dead_code_t.
Referenced by make_pciexbar().
Definition at line 31 of file memmap.c.
References D0F0_PCIEXBAR_LO, die(), HOST_BRIDGE, make_pciexbar(), and pci_read_config32().
Referenced by bootblock_northbridge_init(), and mainboard_romstage_entry().
Definition at line 25 of file memmap.c.
References encode_pciexbar_length().
Referenced by bootblock_northbridge_init(), and mainboard_machine_check().
Definition at line 72 of file memmap.c.
References BIOS_DEBUG, C_BASE_SEG, D_LCK, ESMRAMC, G_SMRAME, PCI_DEV, pci_or_config8(), pci_write_config8(), printk, SMRAMC, and T_EN.