3 #ifndef _QUARK_REG_ACCESS_H_
4 #define _QUARK_REG_ACCESS_H_
32 #define SOC_ACCESS(cmd_, reg_, size_, mask_, value_, timeout_, reg_set_) \
33 _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, SOC_TYPE, \
34 size_, reg_, mask_, value_, timeout_, reg_set_)
37 #define REG_CPU_CR_ACCESS(cmd_, reg_, mask_, value_, timeout_) \
38 SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \
40 #define REG_CPU_CR_READ(reg_) \
41 REG_CPU_CR_ACCESS(READ, reg_, 0, 0, 0)
42 #define REG_CPU_CR_WRITE(reg_, value_) \
43 REG_CPU_CR_ACCESS(WRITE, reg_, 0, value_, 0)
44 #define REG_CPU_CR_AND(reg_, value_) \
45 REG_CPU_CR_RMW(reg_, value_, 0)
46 #define REG_CPU_CR_RMW(reg_, mask_, value_) \
47 REG_CPU_CR_ACCESS(RMW, reg_, mask_, value_, 0)
48 #define REG_CPU_CR_RXW(reg_, mask_, value_) \
49 REG_CPU_CR_ACCESS(RXW, reg_, mask_, value_, 0)
50 #define REG_CPU_CR_OR(reg_, value_) \
51 REG_CPU_CR_RMW(reg_, 0xffffffff, value_)
52 #define REG_CPU_CR_POLL(reg_, mask_, value_, timeout_) \
53 REG_CPU_CR_ACCESS(POLL, reg_, mask_, value_, timeout_)
54 #define REG_CPU_CR_XOR(reg_, value_) \
55 REG_CPU_CR_RXW(reg_, 0xffffffff, value_)
58 #define REG_GPE0_ACCESS(cmd_, reg_, mask_, value_, timeout_) \
59 SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \
61 #define REG_GPE0_READ(reg_) \
62 REG_GPE0_ACCESS(READ, reg_, 0, 0, 0)
63 #define REG_GPE0_WRITE(reg_, value_) \
64 REG_GPE0_ACCESS(WRITE, reg_, 0, value_, 0)
65 #define REG_GPE0_AND(reg_, value_) \
66 REG_GPE0_RMW(reg_, value_, 0)
67 #define REG_GPE0_RMW(reg_, mask_, value_) \
68 REG_GPE0_ACCESS(RMW, reg_, mask_, value_, 0)
69 #define REG_GPE0_RXW(reg_, mask_, value_) \
70 REG_GPE0_ACCESS(RXW, reg_, mask_, value_, 0)
71 #define REG_GPE0_OR(reg_, value_) \
72 REG_GPE0_RMW(reg_, 0xffffffff, value_)
73 #define REG_GPE0_POLL(reg_, mask_, value_, timeout_) \
74 REG_GPE0_ACCESS(POLL, reg_, mask_, value_, timeout_)
75 #define REG_GPE0_XOR(reg_, value_) \
76 REG_GPE0_RXW(reg_, 0xffffffff, value_)
79 #define REG_GPIO_ACCESS(cmd_, reg_, mask_, value_, timeout_) \
80 SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \
82 #define REG_GPIO_READ(reg_) \
83 REG_GPIO_ACCESS(READ, reg_, 0, 0, 0)
84 #define REG_GPIO_WRITE(reg_, value_) \
85 REG_GPIO_ACCESS(WRITE, reg_, 0, value_, 0)
86 #define REG_GPIO_AND(reg_, value_) \
87 REG_GPIO_RMW(reg_, value_, 0)
88 #define REG_GPIO_RMW(reg_, mask_, value_) \
89 REG_GPIO_ACCESS(RMW, reg_, mask_, value_, 0)
90 #define REG_GPIO_RXW(reg_, mask_, value_) \
91 REG_GPIO_ACCESS(RXW, reg_, mask_, value_, 0)
92 #define REG_GPIO_OR(reg_, value_) \
93 REG_GPIO_RMW(reg_, 0xffffffff, value_)
94 #define REG_GPIO_POLL(reg_, mask_, value_, timeout_) \
95 REG_GPIO_ACCESS(POLL, reg_, mask_, value_, timeout_)
96 #define REG_GPIO_XOR(reg_, value_) \
97 REG_GPIO_RXW(reg_, 0xffffffff, value_)
100 #define REG_HOST_BRIDGE_ACCESS(cmd_, reg_, mask_, value_, timeout_) \
101 SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \
103 #define REG_HOST_BRIDGE_READ(reg_) \
104 REG_HOST_BRIDGE_ACCESS(READ, reg_, 0, 0, 0)
105 #define REG_HOST_BRIDGE_WRITE(reg_, value_) \
106 REG_HOST_BRIDGE_ACCESS(WRITE, reg_, 0, value_, 0)
107 #define REG_HOST_BRIDGE_AND(reg_, value_) \
108 REG_HOST_BRIDGE_RMW(reg_, value_, 0)
109 #define REG_HOST_BRIDGE_RMW(reg_, mask_, value_) \
110 REG_HOST_BRIDGE_ACCESS(RMW, reg_, mask_, value_, 0)
111 #define REG_HOST_BRIDGE_RXW(reg_, mask_, value_) \
112 REG_HOST_BRIDGE_ACCESS(RXW, reg_, mask_, value_, 0)
113 #define REG_HOST_BRIDGE_OR(reg_, value_) \
114 REG_HOST_BRIDGE_RMW(reg_, 0xffffffff, value_)
115 #define REG_HOST_BRIDGE_POLL(reg_, mask_, value_, timeout_) \
116 REG_HOST_BRIDGE_ACCESS(POLL, reg_, mask_, value_, timeout_)
117 #define REG_HOST_BRIDGE_XOR(reg_, value_) \
118 REG_HOST_BRIDGE_RXW(reg_, 0xffffffff, value_)
121 #define REG_LEG_GPIO_ACCESS(cmd_, reg_, mask_, value_, timeout_) \
122 SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \
124 #define REG_LEG_GPIO_READ(reg_) \
125 REG_LEG_GPIO_ACCESS(READ, reg_, 0, 0, 0)
126 #define REG_LEG_GPIO_WRITE(reg_, value_) \
127 REG_LEG_GPIO_ACCESS(WRITE, reg_, 0, value_, 0)
128 #define REG_LEG_GPIO_AND(reg_, value_) \
129 REG_LEG_GPIO_RMW(reg_, value_, 0)
130 #define REG_LEG_GPIO_RMW(reg_, mask_, value_) \
131 REG_LEG_GPIO_ACCESS(RMW, reg_, mask_, value_, 0)
132 #define REG_LEG_GPIO_RXW(reg_, mask_, value_) \
133 REG_LEG_GPIO_ACCESS(RXW, reg_, mask_, value_, 0)
134 #define REG_LEG_GPIO_OR(reg_, value_) \
135 REG_LEG_GPIO_RMW(reg_, 0xffffffff, value_)
136 #define REG_LEG_GPIO_POLL(reg_, mask_, value_, timeout_) \
137 REG_LEG_GPIO_ACCESS(POLL, reg_, mask_, value_, timeout_)
138 #define REG_LEG_GPIO_XOR(reg_, value_) \
139 REG_LEG_GPIO_RXW(reg_, 0xffffffff, value_)
142 #define REG_PCIE_AFE_ACCESS(cmd_, reg_, mask_, value_, timeout_) \
143 SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \
145 #define REG_PCIE_AFE_READ(reg_) \
146 REG_PCIE_AFE_ACCESS(READ, reg_, 0, 0, 0)
147 #define REG_PCIE_AFE_WRITE(reg_, value_) \
148 REG_PCIE_AFE_ACCESS(WRITE, reg_, 0, value_, 0)
149 #define REG_PCIE_AFE_AND(reg_, value_) \
150 REG_PCIE_AFE_RMW(reg_, value_, 0)
151 #define REG_PCIE_AFE_RMW(reg_, mask_, value_) \
152 REG_PCIE_AFE_ACCESS(RMW, reg_, mask_, value_, 0)
153 #define REG_PCIE_AFE_RXW(reg_, mask_, value_) \
154 REG_PCIE_AFE_ACCESS(RXW, reg_, mask_, value_, 0)
155 #define REG_PCIE_AFE_OR(reg_, value_) \
156 REG_PCIE_AFE_RMW(reg_, 0xffffffff, value_)
157 #define REG_PCIE_AFE_POLL(reg_, mask_, value_, timeout_) \
158 REG_PCIE_AFE_ACCESS(POLL, reg_, mask_, value_, timeout_)
159 #define REG_PCIE_AFE_XOR(reg_, value_) \
160 REG_PCIE_AFE_RXW(reg_, 0xffffffff, value_)
163 #define MAINBOARD_PCIE_RESET(pin_value_) \
164 SOC_ACCESS(WRITE, 0, REG_SCRIPT_SIZE_32, 1, pin_value_, 0, PCIE_RESET)
167 #define REG_RMU_TEMP_ACCESS(cmd_, reg_, mask_, value_, timeout_) \
168 SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \
170 #define REG_RMU_TEMP_READ(reg_) \
171 REG_RMU_TEMP_ACCESS(READ, reg_, 0, 0, 0)
172 #define REG_RMU_TEMP_WRITE(reg_, value_) \
173 REG_RMU_TEMP_ACCESS(WRITE, reg_, 0, value_, 0)
174 #define REG_RMU_TEMP_AND(reg_, value_) \
175 REG_RMU_TEMP_RMW(reg_, value_, 0)
176 #define REG_RMU_TEMP_RMW(reg_, mask_, value_) \
177 REG_RMU_TEMP_ACCESS(RMW, reg_, mask_, value_, 0)
178 #define REG_RMU_TEMP_RXW(reg_, mask_, value_) \
179 REG_RMU_TEMP_ACCESS(RXW, reg_, mask_, value_, 0)
180 #define REG_RMU_TEMP_OR(reg_, value_) \
181 REG_RMU_TEMP_RMW(reg_, 0xffffffff, value_)
182 #define REG_RMU_TEMP_POLL(reg_, mask_, value_, timeout_) \
183 REG_RMU_TEMP_ACCESS(POLL, reg_, mask_, value_, timeout_)
184 #define REG_RMU_TEMP_XOR(reg_, value_) \
185 REG_RMU_TEMP_RXW(reg_, 0xffffffff, value_)
188 #define REG_SOC_UNIT_ACCESS(cmd_, reg_, mask_, value_, timeout_) \
189 SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \
191 #define REG_SOC_UNIT_READ(reg_) \
192 REG_SOC_UNIT_ACCESS(READ, reg_, 0, 0, 0)
193 #define REG_SOC_UNIT_WRITE(reg_, value_) \
194 REG_SOC_UNIT_ACCESS(WRITE, reg_, 0, value_, 0)
195 #define REG_SOC_UNIT_AND(reg_, value_) \
196 REG_SOC_UNIT_RMW(reg_, value_, 0)
197 #define REG_SOC_UNIT_RMW(reg_, mask_, value_) \
198 REG_SOC_UNIT_ACCESS(RMW, reg_, mask_, value_, 0)
199 #define REG_SOC_UNIT_RXW(reg_, mask_, value_) \
200 REG_SOC_UNIT_ACCESS(RXW, reg_, mask_, value_, 0)
201 #define REG_SOC_UNIT_OR(reg_, value_) \
202 REG_SOC_UNIT_RMW(reg_, 0xffffffff, value_)
203 #define REG_SOC_UNIT_POLL(reg_, mask_, value_, timeout_) \
204 REG_SOC_UNIT_ACCESS(POLL, reg_, mask_, value_, timeout_)
205 #define REG_SOC_UNIT_XOR(reg_, value_) \
206 REG_SOC_UNIT_RXW(reg_, 0xffffffff, value_)
209 #define TIME_DELAY_USEC(value_) \
210 SOC_ACCESS(WRITE, 0, REG_SCRIPT_SIZE_32, 0, value_, 0, \
214 #define REG_USB_ACCESS(cmd_, reg_, mask_, value_, timeout_) \
215 SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \
217 #define REG_USB_READ(reg_) \
218 REG_USB_ACCESS(READ, reg_, 0, 0, 0)
219 #define REG_USB_WRITE(reg_, value_) \
220 REG_USB_ACCESS(WRITE, reg_, 0, value_, 0)
221 #define REG_USB_AND(reg_, value_) \
222 REG_USB_RMW(reg_, value_, 0)
223 #define REG_USB_RMW(reg_, mask_, value_) \
224 REG_USB_ACCESS(RMW, reg_, mask_, value_, 0)
225 #define REG_USB_RXW(reg_, mask_, value_) \
226 REG_USB_ACCESS(RXW, reg_, mask_, value_, 0)
227 #define REG_USB_OR(reg_, value_) \
228 REG_USB_RMW(reg_, 0xffffffff, value_)
229 #define REG_USB_POLL(reg_, mask_, value_, timeout_) \
230 REG_USB_ACCESS(POLL, reg_, mask_, value_, timeout_)
231 #define REG_USB_XOR(reg_, value_) \
232 REG_USB_RXW(reg_, 0xffffffff, value_)
@ REG_SCRIPT_TYPE_SOC_BASE
uint32_t reg_host_bridge_unit_read(uint32_t reg_address)
void mea_write(uint32_t reg_address)
void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address)
uint32_t reg_legacy_gpio_read(uint32_t reg_address)
uint32_t port_reg_read(uint8_t port, uint32_t offset)
void reg_legacy_gpio_write(uint32_t reg_address, uint32_t value)
void mdr_write(uint32_t value)
void mainboard_gpio_pcie_reset(uint32_t pin_value)
void * get_i2c_address(void)
uint32_t reg_rmu_temp_read(uint32_t reg_address)
void port_reg_write(uint8_t port, uint32_t offset, uint32_t value)