coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
pcie_gpp.c
Go to the documentation of this file.
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <
amdblocks/amd_pci_util.h
>
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#include <soc/pci_devs.h>
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/* See AMD PPR 55570 - IOAPIC Initialization for the table that AGESA sets up */
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const
struct
pci_routing_info
pci_routing_table
[] = {
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{
PCIE_GPP_0_DEVFN
, 0,
PCI_SWIZZLE_ABCD
, 0x10},
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{
PCIE_GPP_1_DEVFN
, 1,
PCI_SWIZZLE_ABCD
, 0x11},
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{
PCIE_GPP_2_DEVFN
, 2,
PCI_SWIZZLE_ABCD
, 0x12},
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{
PCIE_GPP_3_DEVFN
, 3,
PCI_SWIZZLE_ABCD
, 0x13},
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{
PCIE_GPP_4_DEVFN
, 4,
PCI_SWIZZLE_ABCD
, 0x10},
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{
PCIE_GPP_5_DEVFN
, 5,
PCI_SWIZZLE_ABCD
, 0x11},
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{
PCIE_GPP_6_DEVFN
, 6,
PCI_SWIZZLE_ABCD
, 0x12},
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{
PCIE_GPP_A_DEVFN
, 7,
PCI_SWIZZLE_ABCD
, 0x13},
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{
PCIE_GPP_B_DEVFN
, 7,
PCI_SWIZZLE_CDAB
, 0x0C},
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};
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const
struct
pci_routing_info
*
get_pci_routing_table
(
size_t
*entries)
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{
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*entries =
ARRAY_SIZE
(
pci_routing_table
);
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return
pci_routing_table
;
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}
ARRAY_SIZE
#define ARRAY_SIZE(a)
Definition:
helpers.h:12
pci_routing_table
const struct pci_routing_info pci_routing_table[]
Definition:
pcie_gpp.c:7
get_pci_routing_table
const struct pci_routing_info * get_pci_routing_table(size_t *entries)
Definition:
pcie_gpp.c:19
PCIE_GPP_B_DEVFN
#define PCIE_GPP_B_DEVFN
Definition:
pci_devs.h:99
amd_pci_util.h
PCI_SWIZZLE_ABCD
@ PCI_SWIZZLE_ABCD
Definition:
amd_pci_util.h:36
PCI_SWIZZLE_CDAB
@ PCI_SWIZZLE_CDAB
Definition:
amd_pci_util.h:38
PCIE_GPP_6_DEVFN
#define PCIE_GPP_6_DEVFN
Definition:
pci_devs.h:49
PCIE_GPP_1_DEVFN
#define PCIE_GPP_1_DEVFN
Definition:
pci_devs.h:29
PCIE_GPP_3_DEVFN
#define PCIE_GPP_3_DEVFN
Definition:
pci_devs.h:37
PCIE_GPP_A_DEVFN
#define PCIE_GPP_A_DEVFN
Definition:
pci_devs.h:56
PCIE_GPP_4_DEVFN
#define PCIE_GPP_4_DEVFN
Definition:
pci_devs.h:41
PCIE_GPP_5_DEVFN
#define PCIE_GPP_5_DEVFN
Definition:
pci_devs.h:45
PCIE_GPP_0_DEVFN
#define PCIE_GPP_0_DEVFN
Definition:
pci_devs.h:25
PCIE_GPP_2_DEVFN
#define PCIE_GPP_2_DEVFN
Definition:
pci_devs.h:33
pci_routing_info
Each PCI bridge has its INTx lines routed to one of the GNB IO-APIC PCI groups.
Definition:
amd_pci_util.h:48
src
soc
amd
picasso
pcie_gpp.c
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