157 #define VID_CAP_FUNC_EN_N (0x1 << 6)
158 #define VID_FIFO_FUNC_EN_N (0x1 << 5)
159 #define AUD_FIFO_FUNC_EN_N (0x1 << 4)
160 #define AUD_FUNC_EN_N (0x1 << 3)
161 #define HDCP_FUNC_EN_N (0x1 << 2)
162 #define SW_FUNC_EN_N (0x1 << 0)
165 #define SSC_FUNC_EN_N (0x1 << 7)
166 #define AUX_FUNC_EN_N (0x1 << 2)
167 #define SERDES_FIFO_FUNC_EN_N (0x1 << 1)
168 #define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0)
171 #define VIDEO_EN (0x1 << 7)
172 #define VIDEO_MUTE (0x1 << 6)
175 #define IN_D_RANGE_MASK (0x1 << 7)
176 #define IN_D_RANGE_SHIFT (7)
177 #define IN_D_RANGE_CEA (0x1 << 7)
178 #define IN_D_RANGE_VESA (0x0 << 7)
179 #define IN_BPC_MASK (0x7 << 4)
180 #define IN_BPC_SHIFT (4)
181 #define IN_BPC_12_BITS (0x3 << 4)
182 #define IN_BPC_10_BITS (0x2 << 4)
183 #define IN_BPC_8_BITS (0x1 << 4)
184 #define IN_BPC_6_BITS (0x0 << 4)
185 #define IN_COLOR_F_MASK (0x3 << 0)
186 #define IN_COLOR_F_SHIFT (0)
187 #define IN_COLOR_F_YCBCR444 (0x2 << 0)
188 #define IN_COLOR_F_YCBCR422 (0x1 << 0)
189 #define IN_COLOR_F_RGB (0x0 << 0)
192 #define IN_YC_COEFFI_MASK (0x1 << 7)
193 #define IN_YC_COEFFI_SHIFT (7)
194 #define IN_YC_COEFFI_ITU709 (0x1 << 7)
195 #define IN_YC_COEFFI_ITU601 (0x0 << 7)
196 #define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4)
197 #define VID_CHK_UPDATE_TYPE_SHIFT (4)
198 #define VID_CHK_UPDATE_TYPE_1 (0x1 << 4)
199 #define VID_CHK_UPDATE_TYPE_0 (0x0 << 4)
202 #define BIST_EN (0x1 << 3)
203 #define BIST_WH_64 (0x1 << 2)
204 #define BIST_WH_32 (0x0 << 2)
205 #define BIST_TYPE_COLR_BAR (0x0 << 0)
206 #define BIST_TYPE_GRAY_BAR (0x1 << 0)
207 #define BIST_TYPE_MOBILE_BAR (0x2 << 0)
210 #define VID_HRES_TH(x) (((x) & 0xf) << 4)
211 #define VID_VRES_TH(x) (((x) & 0xf) << 0)
214 #define F_SEL (0x1 << 4)
215 #define INTERACE_SCAN_CFG (0x1 << 2)
216 #define INTERACD_SCAN_CFG_OFFSET 2
217 #define VSYNC_POLARITY_CFG (0x1 << 1)
218 #define VSYNC_POLARITY_CFG_OFFSET 1
219 #define HSYNC_POLARITY_CFG (0x1 << 0)
220 #define HSYNC_POLARITY_CFG_OFFSET 0
223 #define PD_INC_BG (0x1 << 7)
224 #define PD_EXP_BG (0x1 << 6)
225 #define PD_AUX (0x1 << 5)
226 #define PD_PLL (0x1 << 4)
227 #define PD_CH3 (0x1 << 3)
228 #define PD_CH2 (0x1 << 2)
229 #define PD_CH1 (0x1 << 1)
230 #define PD_CH0 (0x1 << 0)
233 #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6)
234 #define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6)
235 #define LANE3_MAP_LOGIC_LANE_2 (0x2 << 6)
236 #define LANE3_MAP_LOGIC_LANE_3 (0x3 << 6)
237 #define LANE2_MAP_LOGIC_LANE_0 (0x0 << 4)
238 #define LANE2_MAP_LOGIC_LANE_1 (0x1 << 4)
239 #define LANE2_MAP_LOGIC_LANE_2 (0x2 << 4)
240 #define LANE2_MAP_LOGIC_LANE_3 (0x3 << 4)
241 #define LANE1_MAP_LOGIC_LANE_0 (0x0 << 2)
242 #define LANE1_MAP_LOGIC_LANE_1 (0x1 << 2)
243 #define LANE1_MAP_LOGIC_LANE_2 (0x2 << 2)
244 #define LANE1_MAP_LOGIC_LANE_3 (0x3 << 2)
245 #define LANE0_MAP_LOGIC_LANE_0 (0x0 << 0)
246 #define LANE0_MAP_LOGIC_LANE_1 (0x1 << 0)
247 #define LANE0_MAP_LOGIC_LANE_2 (0x2 << 0)
248 #define LANE0_MAP_LOGIC_LANE_3 (0x3 << 0)
251 #define SEL_24M (0x1 << 3)
254 #define VSYNC_DET (0x1 << 7)
255 #define PLL_LOCK_CHG (0x1 << 6)
256 #define SPDIF_ERR (0x1 << 5)
257 #define SPDIF_UNSTBL (0x1 << 4)
258 #define VID_FORMAT_CHG (0x1 << 3)
259 #define AUD_CLK_CHG (0x1 << 2)
260 #define VID_CLK_CHG (0x1 << 1)
261 #define SW_INT (0x1 << 0)
264 #define ENC_EN_CHG (0x1 << 6)
265 #define HW_BKSV_RDY (0x1 << 3)
266 #define HW_SHA_DONE (0x1 << 2)
267 #define HW_AUTH_STATE_CHG (0x1 << 1)
268 #define HW_AUTH_DONE (0x1 << 0)
271 #define AFIFO_UNDER (0x1 << 7)
272 #define AFIFO_OVER (0x1 << 6)
273 #define R0_CHK_FLAG (0x1 << 5)
276 #define PSR_ACTIVE (0x1 << 7)
277 #define PSR_INACTIVE (0x1 << 6)
278 #define SPDIF_BI_PHASE_ERR (0x1 << 5)
279 #define HOTPLUG_CHG (0x1 << 2)
280 #define HPD_LOST (0x1 << 1)
281 #define PLUG (0x1 << 0)
284 #define INT_HPD (0x1 << 6)
285 #define HW_LT_DONE (0x1 << 5)
286 #define SINK_LOST (0x1 << 3)
287 #define LINK_LOST (0x1 << 2)
288 #define RPLY_RECEIV (0x1 << 1)
289 #define AUX_ERR (0x1 << 0)
292 #define SOFT_INT_CTRL (0x1 << 2)
293 #define INT_POL (0x1 << 0)
296 #define DET_STA (0x1 << 2)
297 #define FORCE_DET (0x1 << 1)
298 #define DET_CTRL (0x1 << 0)
301 #define CHA_CRI(x) (((x) & 0xf) << 4)
302 #define CHA_STA (0x1 << 2)
303 #define FORCE_CHA (0x1 << 1)
304 #define CHA_CTRL (0x1 << 0)
307 #define HPD_STATUS (0x1 << 6)
308 #define F_HPD (0x1 << 5)
309 #define HPD_CTRL (0x1 << 4)
310 #define HDCP_RDY (0x1 << 3)
311 #define STRM_VALID (0x1 << 2)
312 #define F_VALID (0x1 << 1)
313 #define VALID_CTRL (0x1 << 0)
316 #define FIX_M_AUD (0x1 << 4)
317 #define ENHANCED (0x1 << 3)
318 #define FIX_M_VID (0x1 << 2)
319 #define M_VID_UPDATE_CTRL (0x3 << 0)
322 #define LDO_OUTPUT_V_SEL_145 (2 << 6)
323 #define KVCO_DEFALUT (1 << 4)
324 #define CHG_PUMP_CUR_SEL_5US (1 << 2)
325 #define V2L_CUR_SEL_1MA (1 << 0)
328 #define LOCK_DET_CNT_SEL_256 (2 << 5)
329 #define LOOP_FILTER_RESET (0 << 4)
330 #define PALL_SSC_RESET (0 << 3)
331 #define LOCK_DET_BYPASS (0 << 2)
332 #define PLL_LOCK_DET_MODE (0 << 1)
333 #define PLL_LOCK_DET_FORCE (0 << 0)
336 #define REGULATOR_V_SEL_950MV (2 << 4)
337 #define STANDBY_CUR_SEL (0 << 3)
338 #define CHG_PUMP_INOUT_CTRL_1200MV (1 << 1)
339 #define CHG_PUMP_INPUT_CTRL_OP (0 << 0)
342 #define SSC_OFFSET (0 << 6)
343 #define SSC_MODE (1 << 4)
344 #define SSC_DEPTH (9 << 0)
347 #define TX_SWING_PRE_EMP_MODE (1 << 7)
348 #define PRE_DRIVER_PW_CTRL1 (0 << 5)
349 #define LP_MODE_CLK_REGULATOR (0 << 4)
350 #define RESISTOR_MSB_CTRL (0 << 3)
351 #define RESISTOR_CTRL (7 << 0)
354 #define DP_AUX_COMMON_MODE (0 << 4)
355 #define DP_AUX_EN (0 << 3)
356 #define AUX_TERM_50OHM (3 << 0)
359 #define DP_BG_OUT_SEL (4 << 4)
360 #define DP_DB_CUR_CTRL (0 << 3)
361 #define DP_BG_SEL (1 << 2)
362 #define DP_RESISTOR_TUNE_BG (2 << 0)
365 #define CH1_CH3_SWING_EMP_CTRL (5 << 4)
366 #define CH0_CH2_SWING_EMP_CTRL (5 << 0)
369 #define SCRAMBLING_DISABLE (0x1 << 5)
370 #define SCRAMBLING_ENABLE (0x0 << 5)
371 #define LINK_QUAL_PATTERN_SET_MASK (0x7 << 2)
372 #define LINK_QUAL_PATTERN_SET_HBR2 (0x5 << 2)
373 #define LINK_QUAL_PATTERN_SET_80BIT (0x4 << 2)
374 #define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2)
375 #define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2)
376 #define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2)
377 #define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0)
378 #define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0)
379 #define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0)
380 #define SW_TRAINING_PATTERN_SET_DISABLE (0x0 << 0)
383 #define HW_LT_ERR_CODE_MASK 0x70
384 #define HW_LT_ERR_CODE_SHIFT 4
385 #define HW_LT_EN (0x1 << 0)
388 #define PLL_LOCK (0x1 << 4)
389 #define F_PLL_LOCK (0x1 << 3)
390 #define PLL_LOCK_CTRL (0x1 << 2)
391 #define POLL_EN (0x1 << 1)
392 #define PN_INV (0x1 << 0)
395 #define AUX_BUSY (0x1 << 4)
396 #define AUX_STATUS_MASK (0xf << 0)
399 #define DEFER_CTRL_EN (0x1 << 7)
400 #define DEFER_COUNT(x) (((x) & 0x7f) << 0)
403 #define AUX_RX_COMM_I2C_DEFER (0x2 << 2)
404 #define AUX_RX_COMM_AUX_DEFER (0x2 << 0)
407 #define BUF_CLR (0x1 << 7)
408 #define BUF_HAVE_DATA (0x1 << 4)
409 #define BUF_DATA_COUNT(x) (((x) & 0xf) << 0)
412 #define AUX_LENGTH(x) (((x - 1) & 0xf) << 4)
413 #define AUX_TX_COMM_MASK (0xf << 0)
414 #define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3)
415 #define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3)
416 #define AUX_TX_COMM_MOT (0x1 << 2)
417 #define AUX_TX_COMM_WRITE (0x0 << 0)
418 #define AUX_TX_COMM_READ (0x1 << 0)
421 #define PD_AUX_IDLE (0x1 << 3)
422 #define ADDR_ONLY (0x1 << 1)
423 #define AUX_EN (0x1 << 0)
426 #define RST_DP_TX (0x1 << 0)
429 #define TX_TERMINAL_CTRL_50_OHM (0x1 << 4)
432 #define DRIVE_DVDD_BIT_1_0625V (0x4 << 5)
433 #define VCO_BIT_600_MICRO (0x5 << 0)
436 #define PD_RING_OSC (0x1 << 6)
437 #define AUX_TERMINAL_CTRL_37_5_OHM (0x0 << 4)
438 #define AUX_TERMINAL_CTRL_45_OHM (0x1 << 4)
439 #define AUX_TERMINAL_CTRL_50_OHM (0x2 << 4)
440 #define AUX_TERMINAL_CTRL_65_OHM (0x3 << 4)
441 #define TX_CUR1_2X (0x1 << 2)
442 #define TX_CUR_16_MA (0x3 << 0)
445 #define DPCD_DPCD_REV (0x0000)
446 #define DPCD_MAX_LINK_RATE (0x0001)
447 #define DPCD_MAX_LANE_COUNT (0x0002)
448 #define DP_MAX_LANE_COUNT_MASK 0x1f
449 #define DP_TPS3_SUPPORTED (1 << 6)
450 #define DP_ENHANCED_FRAME_CAP (1 << 7)
452 #define DPCD_LINK_BW_SET (0x0100)
453 #define DPCD_LANE_COUNT_SET (0x0101)
455 #define DPCD_TRAINING_PATTERN_SET (0x0102)
456 #define DP_TRAINING_PATTERN_DISABLE 0
457 #define DP_TRAINING_PATTERN_1 1
458 #define DP_TRAINING_PATTERN_2 2
459 #define DP_TRAINING_PATTERN_3 3
460 #define DP_TRAINING_PATTERN_MASK 0x3
462 #define DPCD_TRAINING_LANE0_SET (0x0103)
463 #define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
464 #define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
465 #define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
466 #define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0)
467 #define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0)
468 #define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0)
469 #define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0)
471 #define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
472 #define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3)
473 #define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3)
474 #define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3)
475 #define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3)
477 #define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
478 #define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
480 #define DPCD_LANE0_1_STATUS (0x0202)
481 #define DPCD_LANE2_3_STATUS (0x0203)
482 #define DP_LANE_CR_DONE (1 << 0)
483 #define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
484 #define DP_LANE_SYMBOL_LOCKED (1 << 2)
485 #define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE |\
486 DP_LANE_CHANNEL_EQ_DONE |\
487 DP_LANE_SYMBOL_LOCKED)
489 #define DPCD_LANE_ALIGN_STATUS_UPDATED (0x0204)
490 #define DP_INTERLANE_ALIGN_DONE (1 << 0)
491 #define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
492 #define DP_LINK_STATUS_UPDATED (1 << 7)
494 #define DPCD_ADJUST_REQUEST_LANE0_1 (0x0206)
495 #define DPCD_ADJUST_REQUEST_LANE2_3 (0x0207)
496 #define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
497 #define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
498 #define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
499 #define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
500 #define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
501 #define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
502 #define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
503 #define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
505 #define DPCD_TEST_REQUEST (0x0218)
506 #define DPCD_TEST_RESPONSE (0x0260)
507 #define DPCD_TEST_EDID_CHECKSUM (0x0261)
508 #define DPCD_LINK_POWER_STATE (0x0600)
509 #define DP_SET_POWER_D0 0x1
510 #define DP_SET_POWER_D3 0x2
511 #define DP_SET_POWER_MASK 0x3
513 #define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff)
514 #define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff)
515 #define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f)
517 #define STREAM_ON_TIMEOUT 100
518 #define PLL_LOCK_TIMEOUT 10
519 #define DP_INIT_TRIES 10
521 #define EDID_ADDR 0x50
522 #define EDID_LENGTH 0x80
523 #define EDID_HEADER 0x00
524 #define EDID_EXTENSION_FLAG 0x7e
clock_recovery_m_value_type
@ DP_IRQ_TYPE_HP_CABLE_OUT
@ DP_IRQ_TYPE_HP_CABLE_IN
check_member(rk_edp_regs, pll_reg_5, 0xa00)
int rk_edp_get_edid(struct edid *edid)
video_timing_recognition_type
@ VIDEO_TIMING_FROM_REGISTER
@ VIDEO_TIMING_FROM_CAPTURE
u32 spdif_biphase_int_sta
struct rk_edp_regs * regs