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coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
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Go to the source code of this file.
Data Structures | |
struct | rockchip_spi |
Macros | |
#define | SF_READ_DATA_CMD 0x3 |
#define | SPI_DFS_OFFSET 0 /* Data Frame Size */ |
#define | SPI_DFS_MASK 0x3 |
#define | SPI_DFS_4BIT 0x00 |
#define | SPI_DFS_8BIT 0x01 |
#define | SPI_DFS_16BIT 0x02 |
#define | SPI_DFS_RESV 0x03 |
#define | SPI_CFS_OFFSET 2 |
#define | SPI_CFS_MASK 0xF |
#define | SPI_SCPH_OFFSET 6 |
#define | SPI_SCPH_MASK 0x1 |
#define | SPI_SCPH_TOGMID 0 |
#define | SPI_SCPH_TOGSTA 1 |
#define | SPI_SCOL_OFFSET 7 |
#define | SPI_SCOL_MASK 0x1 |
#define | SPI_SCOL_LOW 0 |
#define | SPI_SCOL_HIGH 1 |
#define | SPI_CSM_OFFSET 8 |
#define | SPI_CSM_MASK 0x3 |
#define | SPI_CSM_KEEP 0x00 |
#define | SPI_CSM_HALF 0x01 |
#define | SPI_CSM_ONE 0x02 |
#define | SPI_CSM_RESV 0x03 |
#define | SPI_SSN_DELAY_OFFSET 10 |
#define | SPI_SSN_DELAY_MASK 0x1 |
#define | SPI_SSN_DELAY_HALF 0x00 |
#define | SPI_SSN_DELAY_ONE 0x01 |
#define | SPI_SEM_OFFSET 11 |
#define | SPI_SEM_MASK 0x1 |
#define | SPI_SEM_LITTLE 0x00 |
#define | SPI_SEM_BIG 0x01 |
#define | SPI_FBM_OFFSET 12 |
#define | SPI_FBM_MASK 0x1 |
#define | SPI_FBM_MSB 0x00 |
#define | SPI_FBM_LSB 0x01 |
#define | SPI_HALF_WORLD_TX_OFFSET 13 |
#define | SPI_HALF_WORLD_MASK 0x1 |
#define | SPI_APB_16BIT 0x00 |
#define | SPI_APB_8BIT 0x01 |
#define | SPI_RXDSD_OFFSET 14 |
#define | SPI_RXDSD_MASK 0x3 |
#define | SPI_FRF_OFFSET 16 |
#define | SPI_FRF_MASK 0x3 |
#define | SPI_FRF_SPI 0x00 |
#define | SPI_FRF_SSP 0x01 |
#define | SPI_FRF_MICROWIRE 0x02 |
#define | SPI_FRF_RESV 0x03 |
#define | SPI_TMOD_OFFSET 18 |
#define | SPI_TMOD_MASK 0x3 |
#define | SPI_TMOD_TR 0x00 |
#define | SPI_TMOD_TO 0x01 |
#define | SPI_TMOD_RO 0x02 |
#define | SPI_TMOD_RESV 0x03 |
#define | SPI_OMOD_OFFSET 20 |
#define | SPI_OMOD_MASK 0x1 |
#define | SPI_OMOD_MASTER 0x00 |
#define | SPI_OMOD_SLAVE 0x01 |
#define | TXFLR_LEVEL_MASK 0x3f |
#define | RXFLR_LEVEL_MASK 0x3f |
#define | SR_MASK 0x7f |
#define | SR_BUSY (1 << 0) |
#define | SR_TF_FULL (1 << 1) |
#define | SR_TF_EMPT (1 << 2) |
#define | SR_RF_EMPT (1 << 3) |
#define | SR_RF_FULL (1 << 4) |
#define | SPI_INT_TXEI (1 << 0) |
#define | SPI_INT_TXOI (1 << 1) |
#define | SPI_INT_RXUI (1 << 2) |
#define | SPI_INT_RXOI (1 << 3) |
#define | SPI_INT_RXFI (1 << 4) |
#define | SPI_DMACR_TX_ENABLE (1 << 1) |
#define | SPI_DMACR_RX_ENABLE (1 << 0) |
#define | SPI_CLEAR_INT_ALL (1 << 0) |
#define | SPI_CLEAR_INT_RXUI (1 << 1) |
#define | SPI_CLEAR_INT_RXOI (1 << 2) |
#define | SPI_CLEAR_INT_TXOI (1 << 3) |
Functions | |
check_member (rockchip_spi, rxdr, 0x800) | |
void | rockchip_spi_init (unsigned int bus, unsigned int speed_hz) |
void | rockchip_spi_set_sample_delay (unsigned int bus, unsigned int delay_ns) |
check_member | ( | rockchip_spi | , |
rxdr | , | ||
0x800 | |||
) |
Definition at line 84 of file spi.c.
References ARRAY_SIZE, assert, rockchip_bitbang_slave::clk, rockchip_bitbang_slave::cs, rockchip_spi::ctrlr0, gpio_input(), gpio_output(), rockchip_bitbang_slave::miso, rockchip_bitbang_slave::mosi, rockchip_spi_slave::regs, rkclk_configure_spi(), rockchip_spi_enable_chip(), rockchip_spi_set_clk(), rockchip_spi_slaves, slaves, SPI_CSM_KEEP, SPI_CSM_OFFSET, SPI_DFS_8BIT, SPI_DFS_OFFSET, SPI_FBM_MSB, SPI_FBM_OFFSET, SPI_FIFO_DEPTH, SPI_FRF_OFFSET, SPI_FRF_SPI, SPI_OMOD_MASTER, SPI_OMOD_OFFSET, SPI_SEM_LITTLE, SPI_SEM_OFFSET, SPI_SRCCLK_HZ, SPI_SSN_DELAY_OFFSET, SPI_SSN_DELAY_ONE, and write32().
Referenced by bootblock_mainboard_init(), configure_ec(), configure_spi_flash(), and configure_tpm().
Definition at line 122 of file spi.c.
References ARRAY_SIZE, assert, clrsetbits32, DIV_ROUND_CLOSEST, GHz, rockchip_spi_slave::regs, rockchip_spi_slaves, SPI_RXDSD_MASK, SPI_RXDSD_OFFSET, and SPI_SRCCLK_HZ.
Referenced by configure_spi_flash().