coreboot
coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers.
bootblock.c
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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <bootblock_common.h>
4 #include <soc/gpio.h>
7 #include "include/gpio.h"
8 
9 static void early_config_superio(void)
10 {
11  const pnp_devfn_t serial_dev = PNP_DEV(0x2e, NCT6791D_SP1);
12  nuvoton_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
13 }
14 
15 static void early_config_gpio(void)
16 {
17  /* This is a hack for FSP because it does things in MemoryInit()
18  * which it shouldn't do. We have to prepare certain gpios here
19  * because of the brokenness in FSP. */
21 }
22 
24 {
26 }
27 
29 {
31 }
static const struct pad_config early_gpio_table[]
Definition: gpio_early.c:7
#define ARRAY_SIZE(a)
Definition: helpers.h:12
__weak void bootblock_mainboard_init(void)
Definition: bootblock.c:19
__weak void bootblock_mainboard_early_init(void)
Definition: bootblock.c:16
static void early_config_superio(void)
Definition: bootblock.c:9
static void early_config_gpio(void)
Definition: bootblock.c:15
#define NCT6791D_SP1
Definition: nct6791d.h:8
void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase)
Definition: early_serial.c:48
#define PNP_DEV(PORT, FUNC)
Definition: pnp_type.h:10
u32 pnp_devfn_t
Definition: pnp_type.h:8
void gpio_configure_pads(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
program a particular set of GPIO
Definition: gpio.c:307